Manoj Kumar Majumder

Orcid: 0000-0002-6928-8191

According to our database1, Manoj Kumar Majumder authored at least 26 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Crosstalk and Power Analysis in Tapered based Composite Cu-CNT TSV in 3D IC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Implementation of Floating Charged Memristor Emulator utilizing DVCCTA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2022
Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021
Role of Through Silicon Via in 3D Integration: Impact on Delay and Power.
J. Circuits Syst. Comput., 2021

Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.
Int. J. Circuit Theory Appl., 2021

2020
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.
Int. J. Circuit Theory Appl., 2020

Performance analysis of mixed CNT bundle interconnects at 10 nm technology.
IET Circuits Devices Syst., 2020

Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.
IET Circuits Devices Syst., 2020

Signal Transmission and Reflection Losses of Cylindrical and Tapered shaped TSV in 3D Integrated Circuits.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.
IET Circuits Devices Syst., 2019

Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Designing SRAM Using CMOS and CNTFET at 32 nm Technology.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018
Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2015
Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect.
J. Circuits Syst. Comput., 2015

2014
Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects.
Microelectron. Reliab., 2014

2013
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects.
Proceedings of the Second International Conference on Soft Computing for Problem Solving, 2012

Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

Novel VLSI architecture for two-dimensional radon transform computations.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012


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