Manoel Eusébio de Lima
According to our database1,
Manoel Eusébio de Lima
authored at least 33 papers
between 2002 and 2018.
Collaborative distances:
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Bibliography
2018
Automatic Segmentation of Neonates Thermal Imaging for Evaluation of Trunk Thermal Asymmetry.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018
2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
A hardware accelerator for the alignment of multiple DNA sequences in forensic identification.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016
2015
An inter-FPGA communication bus with error detection and dynamic clock phase adjustment.
J. Braz. Comput. Soc., 2015
2013
Design of a Self-standing Multimedia Enriched Projector to enhance teaching experience in classroom in Brazilian public schools.
Revista Brasileira de Informática na Educ., 2013
Performance and energy consumption analysis of a seismic application for three different architectures intended for oil and gas industry.
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
2012
An Optimization Mechanism Intended for Static Power Reduction Using Dual-VthTechnique.
J. Electr. Comput. Eng., 2012
Int. J. High Perform. Syst. Archit., 2012
Proceedings of the 41st International Conference on Parallel Processing Workshops, 2012
2011
Label-Free Electrochemical Detection of the Specific Oligonucleotide Sequence of Dengue Virus Type 1 on Pencil Graphite Electrodes.
Sensors, 2011
Int. J. Reconfigurable Comput., 2011
Poster: high performance FPGA-based implementation of the seismic modeling of the RTM algorithm.
Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2011
An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
2009
Architecture for dense matrix multiplication on a high-performance reconfigurable system.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
2008
Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
2006
Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption.
Proceedings of the 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 2006
Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Des. Autom. Embed. Syst., 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005
A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003
2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002