Manish Vachharajani

According to our database1, Manish Vachharajani authored at least 32 papers between 2000 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2012
Reliability Modeling and Management of Nanophotonic On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
Automatic Generation of Multicore Chemical Kernels.
IEEE Trans. Parallel Distributed Syst., 2011

Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication.
ACM J. Emerg. Technol. Comput. Syst., 2011

2010
Global On-Chip Coordination at Light Speed.
IEEE Des. Test Comput., 2010

Power-efficient variation-aware photonic on-chip network management.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Large program trace analysis and compression with ZDDs.
Proceedings of the CGO 2010, 2010

An efficient software transactional memory using commit-time invalidation.
Proceedings of the CGO 2010, 2010

2009
Multi-core acceleration of chemical kinetics for simulation and prediction.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

A high-performance low-power nanophotonic on-chip network.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

An efficient lock-aware transactional memory implementation.
Proceedings of the 4th workshop on the Implementation, 2009

Spectrum: a hybrid nanophotonic-electric on-chip network.
Proceedings of the 46th Design Automation Conference, 2009

2008
Gpu Acceleration of Numerical Weather Prediction.
Parallel Process. Lett., 2008

FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue.
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2008

Gradual typing with unification-based inference.
Proceedings of the 2008 Symposium on Dynamic Languages, 2008

Visualizing potential parallelism in sequential programs.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Frame shared memory: line-rate networking on commodity hardware.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

FastForward for Efficient Pipeline Parallelism.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
The Liberty Simulation Environment: A deliberate approach to high-level system modeling.
ACM Trans. Comput. Syst., 2006

A Case for Compressing Traces with BDDs.
IEEE Comput. Archit. Lett., 2006

2005
Chip multi-processor scalability for single-threaded applications.
SIGARCH Comput. Archit. News, 2005

Compiler Optimization-Space Exploration.
J. Instr. Level Parallelism, 2005

Achieving Structural and Composable Modeling of Complex Systems.
Int. J. Parallel Program., 2005

2004
The Liberty Simulation Environment, version 1.0.
SIGMETRICS Perform. Evaluation Rev., 2004

The liberty structural specification language: a high-level modeling language for component reuse.
Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, 2004

RIFLE: An Architectural Framework for User-Centric Information-Flow Security.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Facilitating reuse in hardware models with enhanced type inference.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Decoupled Software Pipelining with the Synchronization Array.
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004

2003
The liberty simulation environment as a pedagogical tool.
Proceedings of the 2003 workshop on Computer architecture education, 2003

Compiler Optimization-Space Exploration.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002
Microarchitectural exploration with Liberty.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Design Tools for Application Specific Embedded Processors.
Proceedings of the Embedded Software, Second International Conference, 2002

2000
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.
Proceedings of the 2000 International Conference on Compilers, 2000


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