Manil Dev Gomony

Orcid: 0000-0002-5889-0785

According to our database1, Manil Dev Gomony authored at least 26 papers between 2012 and 2024.

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Bibliography

2024
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Hardware-aware training of models with synaptic delays for digital event-driven neuromorphic processors.
CoRR, 2024

Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Invited: Achieving PetaOps/W Edge-AI Processing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Dependability of Future Edge-AI Processors: Pandora's Box.
Proceedings of the IEEE European Test Symposium, 2023


2022
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

THOR - A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency.
CoRR, 2022

CONVOLVE: Smart and seamless design of smart edge processors.
CoRR, 2022

BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC.
CoRR, 2022

The Hardware Foundation of 6G: The NEW-6G Approach.
Proceedings of the 2022 Joint European Conference on Networks and Communications & 6G Summit, 2022

2021
Digital Predistortion with Compressed Observations for Cloud-Based Learning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

2020
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Towards ASIP Architecture-Driven Algorithm Development.
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019

A Reconfigurable Architecture for Posit Arithmetic.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Quater-imaginary base for complex number arithmetic circuits.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems.
IEEE Trans. Computers, 2017

2015
A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels.
ACM Trans. Embed. Comput. Syst., 2015

A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Rev., 2013

Architecture and optimal configuration of a real-time multi-channel memory controller.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Leveraging 802.11n frame aggregation to enhance QoS and power consumption in Wi-Fi networks.
Comput. Networks, 2012

DRAM selection and configuration for real-time mobile systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012


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