Mandalagiri S. Chandrasekhar

According to our database, Mandalagiri S. Chandrasekhar authored at least 5 papers between 1982 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

1997

Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits.

Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace

VLSI Design, 1997

1990

High-Level Delay Estimation for Technology-Independent Logic Equations.

David E. Wallace, Mandalagiri S. Chandrasekhar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

Optimal routing of two rectangular blocks.

Mandalagiri S. Chandrasekhar, Melvin A. Breuer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1987

Application of Term Rewriting Techniques to Hardware Design Verification.

Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1982

Optimum placement of two rectangular blocks.

Mandalagiri S. Chandrasekhar, Melvin A. Breuer

Proceedings of the 19th Design Automation Conference, 1982