Manash Chanda
Orcid: 0000-0002-6914-9474
According to our database1,
Manash Chanda
authored at least 10 papers
between 2014 and 2023.
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Collaborative distances:
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Bibliography
2023
A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications.
Microelectron. J., March, 2023
2022
Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor.
Comput. Electr. Eng., 2022
Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime.
Comput. Electr. Eng., 2022
2021
Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm.
IEEE Trans. Artif. Intell., 2021
2020
IET Circuits Devices Syst., 2020
2018
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing.
IET Circuits Devices Syst., 2018
2017
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application.
J. Low Power Electron., 2017
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application.
J. Circuits Syst. Comput., 2015
2014
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014