Mamidala Jagadesh Kumar

According to our database, Mamidala Jagadesh Kumar authored at least 12 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study.

Aakash Kumar Jain, Mamidala Jagadesh Kumar

IEEE Access, 2020

2017

Double gate symmetric tunnel FET: investigation and analysis.

Sindhu Ramaswamy, Mamidala Jagadesh Kumar

IET Circuits Devices Syst., 2017

Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs.

Shubham Sahay, Mamidala Jagadesh Kumar

IEEE Access, 2017

DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions.

Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2012

Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model.

Tarun Kumar Agarwal, Mamidala Jagadesh Kumar

Proceedings of the 25th International Conference on VLSI Design, 2012

2010

A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications.

Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2007

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation.

Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2004

Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study.

G. Venkateshwar Reddy, Mamidala Jagadesh Kumar

Microelectron. J., 2004

A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors.

Mamidala Jagadesh Kumar, Vinod Parihar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI.

Mamidala Jagadesh Kumar, Linga Reddy Cenkeramaddi

Microelectron. Reliab., 2003

A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design.

Mamidala Jagadesh Kumar, D. Venkateshrao

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET.

Mamidala Jagadesh Kumar, Vikram Verma

IEEE Trans. Reliab., 2002