Malte Baesler
Orcid: 0000-0003-2108-308X
According to our database1,
Malte Baesler
authored at least 8 papers
between 2009 and 2013.
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Bibliography
2013
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs.
Int. J. Reconfigurable Comput., 2013
2012
FPGA implementation of a decimal floating-point co-processor with accurate scalar product unit.
PhD thesis, 2012
2011
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
2010
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing.
J. Syst. Archit., 2010
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA.
Int. J. Reconfigurable Comput., 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2009
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009