Malgorzata Marek-Sadowska

According to our database, Malgorzata Marek-Sadowska authored at least 238 papers between 1983 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

ISPD 2023 Lifetime Achievement Award Bio.

Malgorzata Marek-Sadowska

Proceedings of the 2023 International Symposium on Physical Design, 2023

2019

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration.

Ali Abbasinasab, Malgorzata Marek-Sadowska

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators.

Ping-Lin Yang, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2018

RAIN: a tool for reliability assessment of interconnect networks - physics to software.

Ali Abbasinasab, Malgorzata Marek-Sadowska

Proceedings of the 55th Annual Design Automation Conference, 2018

2016

Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence.

Zhong Guan, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2016

AFD-based method for signal line EM reliability evaluation.

Zhong Guan, Malgorzata Marek-Sadowska

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A fast, fully verifiable, and hardware predictable ASIC design methodology.

Ping-Lin Yang, Malgorzata Marek-Sadowska

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Making split-fabrication more secure.

Ping-Lin Yang, Malgorzata Marek-Sadowska

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation.

Zhong Guan, Malgorzata Marek-Sadowska

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips.

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly

IEEE Trans. Very Large Scale Integr. Syst., 2015

T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool.

Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures.

Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif

IEEE Trans. Very Large Scale Integr. Syst., 2015

Machine Learning in Simulation-Based Analysis.

Li-C. Wang, Malgorzata Marek-Sadowska

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Blech Effect in Interconnects: Applications and Design Guidelines.

Ali Abbasinasab, Malgorzata Marek-Sadowska

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

2014

Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure.

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study.

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

IEEE Comput. Archit. Lett., 2014

Estimating true worst currents for power grid electromigration analysis.

Di-An Li, Malgorzata Marek-Sadowska

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Statistical analysis of process variation induced SRAM electromigration degradation.

Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs.

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Routing Challenges for Designs With Super High Pin Density.

Xiang Qiu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

SRAM bit-line electromigration mechanism and its prevention scheme.

Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif

Proceedings of the International Symposium on Quality Electronic Design, 2013

Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure.

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly

Proceedings of the International Symposium on Physical Design, 2013

2012

A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures.

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs.

Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Vertical Slit Field Effect Transistor in ultra-low power applications.

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Can pin access limit the footprint scaling?

Xiang Qiu, Malgorzata Marek-Sadowska

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Power Delivery for Multicore Systems.

Aida Todri, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2011

Reliability Analysis and Optimization of Power-Gated ICs.

Aida Todri, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2011

Performance Optimization Using Variable-Latency Design Style.

Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2011

On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits.

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Metrics for characterizing machine learning-based hotspot detection methods.

Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

On old and new routing problems.

Malgorzata Marek-Sadowska

Proceedings of the 2011 International Symposium on Physical Design, 2011

Low power, high throughput network-on-chip fabric for 3D multicore processors.

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Variation-aware electromigration analysis of power/ground networks.

Di-An Li, Malgorzata Marek-Sadowska

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Layout effects in fine grain 3D integrated regular microprocessor blocks.

Vivek S. Nandakumar, Malgorzata Marek-Sadowska

Proceedings of the 48th Design Automation Conference, 2011

Rapid layout pattern classification.

Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Layout Generator for Transistor-Level High-Density Regular Circuits.

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On-chip em-sensitive interconnect structures.

Di-An Li, Malgorzata Marek-Sadowska, Bill Lee

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Statistical static timing analysis flow for transistor level macros in a microprocessor.

Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Performance study of VeSFET-based, high-density regular circuits.

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly

Proceedings of the 2010 International Symposium on Physical Design, 2010

2009

Timing-Aware Multiple-Delay-Fault Diagnosis.

Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Spare Cells With Constant Insertion for Engineering Change.

Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A study of decoupling capacitor effectiveness in power and ground grid networks.

Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Transistor-level layout of high-density regular circuits.

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly

Proceedings of the 2009 International Symposium on Physical Design, 2009

Electromigration study of power-gated grids.

Aida Todri, Malgorzata Marek-Sadowska

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

Improving the Resolution of Single-Delay-Fault Diagnosis.

Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Timing analysis considering IR drop waveforms in power gating designs.

Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 26th International Conference on Computer Design, 2008

A study of reliability issues in clock distribution networks.

Aida Todri, Malgorzata Marek-Sadowska

Proceedings of the 26th International Conference on Computer Design, 2008

ECO-Map: Technology remapping for post-mask ECO using simulated annealing.

Nilesh Modi, Malgorzata Marek-Sadowska

Proceedings of the 26th International Conference on Computer Design, 2008

Is there always performance overhead for regular fabric?

Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz

Proceedings of the 26th International Conference on Computer Design, 2008

Power supply noise aware workload assignment for multi-core systems.

Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Power gating scheduling for power/ground noise reduction.

Hailin Jiang, Malgorzata Marek-Sadowska

Proceedings of the 45th Design Automation Conference, 2008

2007

Timing-Aware Power-Noise Reduction in Placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Power-Gating Aware Floorplanning.

Hailin Jiang, Malgorzata Marek-Sadowska

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Electromigration and voltage drop aware power grid optimization for power gated ICs.

Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Analysis and optimization of power-gated ICs with multiple power gating configurations.

Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Engineering change using spare cells with constant insertion.

Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.

Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 44th Design Automation Conference, 2007

OPC-Free and Minimally Irregular IC Design Style.

Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska

Proceedings of the 44th Design Automation Conference, 2007

mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.

Yajun Ran, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2006

Designing via-configurable logic blocks for regular fabric.

Yajun Ran, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2006

Analysis and methodology for multiple-fault diagnosis.

Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Semi-Individual Wire-Length Prediction With Application to Logic Synthesis.

Qinghua Liu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology.

Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

Proceedings of the 2006 IEEE International Test Conference, 2006

Analysis of Process Variation's Effect on SRAM's Read Stability.

Chung-Kuan Tsai, Malgorzata Marek-Sadowska

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Delay Fault Diagnosis for Non-Robust Test.

Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Power/ground supply network optimization for power-gating.

Hailin Jiang, Malgorzata Marek-Sadowska

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

General skew constrained clock network sizing based on sequential linear programming.

Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Delay-fault diagnosis using timing information.

Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

On-chip power-supply network optimization using multigrid-based technique.

Kai Wang, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Eliminating false positives in crosstalk noise analysis.

Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A study of netlist structure and placement efficiency.

Qinghua Liu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Multilevel fixed-point-addition-based VLSI placement.

Bo Hu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis.

Chung-Kuan Tsai, Malgorzata Marek-Sadowska

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Wire length prediction-based technology mapping and fanout optimization.

Qinghua Liu, Malgorzata Marek-Sadowska

Proceedings of the 2005 International Symposium on Physical Design, 2005

mFAR: fixed-points-addition-based VLSI placement algorithm.

Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska

Proceedings of the 2005 International Symposium on Physical Design, 2005

Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement.

Qinghua Liu, Malgorzata Marek-Sadowska

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Benefits and Costs of Power-Gating Technique.

Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Timing-aware power noise reduction in layout.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A congestion-driven placement framework with local congestion prediction.

Qinghua Liu, Malgorzata Marek-Sadowska

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Clock skew bounds estimation under power supply and process variations.

Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Skew-programmable clock design for FPGA and skew-aware placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Sequential delay budgeting with interconnect prediction.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2004

Individual wire-length prediction with application to timing-driven placement.

Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2004

Fine granularity clustering-based placement.

Bo Hu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Fast postplacement optimization using functional symmetries.

Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Pipelining Sequential Circuits with Wave Steering.

Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 2004

Clock network sizing via sequential linear programming with time-domain analysis.

Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 2004 International Symposium on Physical Design, 2004

Diagnosis of Hold Time Defects.

Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Potential Slack Budgeting with Clock Skew Optimization.

Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

The Magic of a Via-Configurable Regular Fabric.

Yajun Ran, Malgorzata Marek-Sadowska

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

An integrated design flow for a via-configurable gate array.

Yajun Ran, Malgorzata Marek-Sadowska

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Multilevel expansion-based VLSI placement with blockages.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Eliminating False Positives in Crosstalk Noise Analysis.

Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska

Proceedings of the 2004 Design, 2004

Buffer sizing for clock power minimization subject to general skew constraints.

Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 41th Design Automation Conference, 2004

On designing via-configurable cell blocks for regular fabrics.

Yajun Ran, Malgorzata Marek-Sadowska

Proceedings of the 41th Design Automation Conference, 2004

Pre-layout wire length and congestion estimation.

Qinghua Liu, Malgorzata Marek-Sadowska

Proceedings of the 41th Design Automation Conference, 2004

Designing a via-configurable regular fabric.

Yajun Ran, Malgorzata Marek-Sadowska

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

PITIA: an FPGA for throughput-intensive applications.

Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2003

Wave steering to integrate logic and physical syntheses.

Arindam Mukherjee, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2003

Buffer delay change in the presence of power and ground noise.

Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer

IEEE Trans. Very Large Scale Integr. Syst., 2003

A new reasoning scheme for efficient redundancy addition and removal.

Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Clock and Power Gating with Timing Closure.

Arindam Mukherjee, Malgorzata Marek-Sadowska

IEEE Des. Test Comput., 2003

Wire length prediction in constraint driven placement.

Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

An Efficient and Effective Methodology on the Multiple Fault Diagnosis.

Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Modeling Crosstalk Induced Delay.

Chung-Kuan Tsai, Malgorzata Marek-Sadowska

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Minimizing Inter-Clock Coupling Jitter.

Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Fine granularity clustering for large scale placement problems.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the 2003 International Symposium on Physical Design, 2003

Synthesis and placement flow for gain-based programmable regular fabrics.

Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska

Proceedings of the 2003 International Symposium on Physical Design, 2003

Minimizing coupling jitter by buffer resizing for coupled clock networks.

Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A crosstalk aware two-pin net router.

Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Multiple Fault Diagnosis Using n-Detection Tests.

Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Minimum-Area Sequential Budgeting for FPGA.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Power/Ground Mesh Area Optimization Using Multigrid-Based Technique.

Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 2003 Design, 2003

Delay budgeting in sequential circuit with application on FPGA placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Crosstalk noise in FPGAs.

Yajun Ran, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Gain-based technology mapping for discrete-size cell libraries.

Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Wire length prediction based clustering and its application in placement.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

Temporofunctional crosstalk noise analysis.

Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003

2002

Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis.

Tong Xiao, Malgorzata Marek-Sadowska

VLSI Design, 2002

Efficient circuit clustering for area and power reduction in FPGAs.

Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska

ACM Trans. Design Autom. Electr. Syst., 2002

FPGA interconnect planning.

Amit Singh, Malgorzata Marek-Sadowska

Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Efficient Closed-Form Crosstalk Delay Metrics.

Lauren Hui Chen, Malgorzata Marek-Sadowska

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

FAR: fixed-points addition & relaxation based placement.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of 2002 International Symposium on Physical Design, 2002

Incremental delay change due to crosstalk noise.

Lauren Hui Chen, Malgorzata Marek-Sadowska

Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion minimization during placement without estimation.

Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

ATPG-based logic synthesis: an overview.

Chih-Wei Jim Chang, Malgorzata Marek-Sadowska

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Efficient circuit clustering for area and power reduction in FPGAs.

Amit Singh, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.

Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska

Proceedings of the 2002 Design, 2002

Closed-Form Crosstalk Noise Metrics for Physical Design Applications.

Lauren Hui Chen, Malgorzata Marek-Sadowska

Proceedings of the 2002 Design, 2002

Coping with buffer delay change due to power and ground noise.

Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer

Proceedings of the 39th Design Automation Conference, 2002

2001

Aggressor alignment for worst-case crosstalk noise.

Lauren Hui Chen, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect complexity-aware FPGA placement using Rent's rule.

Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Gate Sizing to Eliminate Crosstalk Induced Timing Violation.

Tong Xiao, Malgorzata Marek-Sadowska

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Interconnect Resource-Aware Placement for Hierarchical FPGAs.

Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Single-Pass Redundancy Addition and Removal.

Chih-Wei Jim Chang, Malgorzata Marek-Sadowska

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Who are the alternative wires in your neighborhood? (alternative wires identification without search).

Chih-Wei Jim Chang, Malgorzata Marek-Sadowska

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Interconnect pipelining in a throughput-intensive FPGA architecture.

Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

A Global Routing Technique for Wave-Steering Design Methodology.

Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

In-place delay constrained power optimization using functional symmetries.

Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification.

Tong Xiao, Malgorzata Marek-Sadowska

Proceedings of the 38th Design Automation Conference, 2001

Latency and Latch Count Minimization in Wave Steered Circuits.

Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska

Proceedings of the 38th Design Automation Conference, 2001

Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques.

Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska

Proceedings of the 38th Design Automation Conference, 2001

2000

Star test: the theory and its applications.

Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

OBDD Minimization Based on Two-Level Representation of Boolean Functions.

Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong

IEEE Trans. Computers, 2000

Efficient Delay Calculation in Presence of Crosstalk.

Tong Xiao, Malgorzata Marek-Sadowska

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Aggressor alignment for worst-case coupling noise.

Lauren Hui Chen, Malgorzata Marek-Sadowska

Proceedings of the 2000 International Symposium on Physical Design, 2000

Worst Delay Estimation in Crosstalk Aware Static Timing Analysis.

Tong Xiao, Malgorzata Marek-Sadowska

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A novel high throughput reconfigurable FPGA architecture.

Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Wave Steered FSMs.

Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska

Proceedings of the 2000 Design, 2000

Wave-steering one-hot encoded FSMs.

Luca Macchiarulo, Malgorzata Marek-Sadowska

Proceedings of the 37th Conference on Design Automation, 2000

Fast post-placement rewiring using easily detectable functional symmetries.

Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska

Proceedings of the 37th Conference on Design Automation, 2000

1999

Crosstalk in VLSI interconnections.

Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Logic synthesis for engineering change.

Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.

Douglas Chang, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1999

Circuit Optimization by Rewiring.

Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1999

Modeling Crosstalk in Resistive VLSI Interconnections.

Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

STAR-ATPG: a high speed test pattern generator for large scan designs.

Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Circuit clustering using graph coloring.

Amit Singh, Malgorzata Marek-Sadowska

Proceedings of the 1999 International Symposium on Physical Design, 1999

Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique.

Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long

Proceedings of the 36th Conference on Design Automation, 1999

Wave pipelining YADDs-a feasibility study.

Arindam Mukherjee, Malgorzata Marek-Sadowska, Stephen I. Long

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

Crosstalk Reduction by Transistor Sizing.

Tong Xiao, Malgorzata Marek-Sadowska

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Power Distribution Synthesis for VLSI.

Ashok Vittal, Malgorzata Marek-Sadowska

VLSI Design, 1998

Cost-free scan: a low-overhead scan path design.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Test-point insertion: scan paths through functional logic.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A hybrid methodology for switching activities estimation.

David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs.

Douglas Chang, Malgorzata Marek-Sadowska

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Functional Scan Chain Testing.

Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee

Proceedings of the 1998 Design, 1998

1997

Routing for array-type FPGA's.

Yu-Liang Wu, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Low-power buffered clock tree design.

Ashok Vittal, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Crosstalk reduction for VLSI.

Ashok Vittal, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On designing universal logic blocks and their application to FPGA design.

Chih-Chang Lin, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Postlayout logic restructuring using alternative wires.

Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Boolean Functions Classification via Fixed Polarity Reed-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1997

Scan-Encoded Test Pattern Generation for BIST.

Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Decomposition of Multiple-Valued Relations .

Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations.

Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs.

Douglas Chang, Malgorzata Marek-Sadowska

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

STARBIST: Scan Autocorrelated Random Pattern Generation.

Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska

Proceedings of the 34st Conference on Design Automation, 1997

Post-Layout Logic Restructuring for Performance Optimization.

Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska

Proceedings of the 34st Conference on Design Automation, 1997

A Test Synthesis Approach to Reducing BALLAST DFT Overhead.

Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng

Proceedings of the 34st Conference on Design Automation, 1997

Not necessarily more switches more routability [sic.].

Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Graph based analysis of 2-D FPGA routing.

Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.

Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Perturb and simplify: multilevel Boolean network optimizer.

Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Generalized Reed-Muller Forms as a Tool to Detect Symmetries.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

IEEE Trans. Computers, 1996

Clock skew optimization for ground bounce control.

Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Fast Boolean optimization by rewiring.

Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Logic Synthesis for Testability.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Sequential Permissible Functions and their Application to Circuit Optimization.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee

Proceedings of the 1996 European Design and Test Conference, 1996

Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares.

Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 1996 European Design and Test Conference, 1996

Multilevel Logic Synthesis for Arithmetic Functions.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 33st Conference on Design Automation, 1996

Test Point Insertion: Scan Paths through Combinational Logic.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee

Proceedings of the 33st Conference on Design Automation, 1996

A New Hybrid Methodology for Power Estimation.

David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska

Proceedings of the 33st Conference on Design Automation, 1996

1995

The crossing distribution problem [IC layout].

Malgorzata Marek-Sadowska, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Cost-free scan: a low-overhead scan path design methodology.

Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Circuit partitioning with logic perturbation.

David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing.

Yu-Liang Wu, Malgorzata Marek-Sadowska

Proceedings of the 32st Conference on Design Automation, 1995

Power Distribution Topology Design.

Ashok Vittal, Malgorzata Marek-Sadowska

Proceedings of the 32st Conference on Design Automation, 1995

Power Optimal Buffered Clock Tree Design.

Ashok Vittal, Malgorzata Marek-Sadowska

Proceedings of the 32st Conference on Design Automation, 1995

Logic Synthesis for Engineering Change.

Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

Proceedings of the 32st Conference on Design Automation, 1995

An Efficient Algorithm for Local Don't Care Sets Calculation.

Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng

Proceedings of the 32st Conference on Design Automation, 1995

Routing on regular segmented 2-D FPGAs.

Yu-Liang Wu, Malgorzata Marek-Sadowska

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

Logic rectification and synthesis for engineering change.

Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

On the Verification of Function Equivalence with unknown Input Correspondence.

David Ihsin Cheng, Malgorzata Marek-Sadowska

J. Circuits Syst. Comput., 1994

Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Universal logic gate for FPGA design.

Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Perturb and simplify: multi-level boolean network optimizer.

Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

On computational complexity of a detailed routing problem in two dimensional FPGAs.

Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

An Efficient Router for 2-D Field Programmable Gate Arrays.

Yu-Liang Wu, Malgorzata Marek-Sadowska

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.

Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Minimal Delay Interconnect Design Using Alphabetic Trees.

Ashok Vittal, Malgorzata Marek-Sadowska

Proceedings of the 31st Conference on Design Automation, 1994

Boolean Matching Using Generalized Reed-Muller Forms.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the 31st Conference on Design Automation, 1994

Layout Driven Logic Synthesis for FPGAs.

Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska

Proceedings of the 31st Conference on Design Automation, 1994

1993

Stepwise equivalent conductance circuit simulation technique.

Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Efficient minimization algorithms for fixed polarity AND/XOR canonical networks.

Chien-Chung Tsai, Malgorzata Marek-Sadowska

Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

Graph based analysis of FPGA routing.

Yu-Liang Wu, Malgorzata Marek-Sadowska

Proceedings of the European Design Automation Conference 1993, 1993

Issues in Timing Driven Layout.

Malgorzata Marek-Sadowska

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992

Algorithm for wire sizing of Power and Ground Networks in VLSI Designs.

Robi Dutta, Malgorzata Marek-Sadowska

J. Circuits Syst. Comput., 1992

Switch box routing: a retrospective.

Malgorzata Marek-Sadowska

Integr., 1992

A New Accurate and Efficient Timing Simulator.

Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska

Proceedings of the Fifth International Conference on VLSI Design, 1992

Technology Mapping via Transformations of Function Graphs.

Shih-Chieh Chang, Malgorzata Marek-Sadowska

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

The Crossing Distribution Problem.

Malgorzata Marek-Sadowska, Majid Sarrafzadeh

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits.

Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh

Proceedings of the conference on European design automation, 1991

A fast and efficient algorithm for determining fanout trees in large networks.

Shen Lin, Malgorzata Marek-Sadowska

Proceedings of the conference on European design automation, 1991

1990

Pin assignment for improved performance in standard cell design.

Malgorzata Marek-Sadowska, Shen P. Lin

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Floorplanning with Pin Assignment.

Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Delay and Area Optimization in Standard-Cell Design.

Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic.

Fillia Makedon, Malgorzata Marek-Sadowska

Proceedings of the Computer Assisted Learning, 2nd International Conference, 1989

Timing driven placement.

Malgorzata Marek-Sadowska, Shen Lin

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Automatic Sizing of Power/Ground (P/G) Networks in VLSI.

Rajiv Dutta, Malgorzata Marek-Sadowska

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987

Pad Assignment for Power Nets in VLSI Circuits.

Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1985

Two-dimensional router for double layer layout.

Malgorzata Marek-Sadowska

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

An Efficient Single-Row Routing Algorithm.

Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

An Unconstrained Topological Via Minimization Problem for Two-Layer Routing.

Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

Global Routing for Gate Array.

Jeong-Tyng Li, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1983

Single-Layer Routing for VLSI: Analysis and Algorithms.

Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983