Malgorzata Chrzanowska-Jeske

According to our database, Malgorzata Chrzanowska-Jeske authored at least 75 papers between 1990 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

SERS-3DPlace: Ensemble Reinforcement Learning for 3D Monolithic Placement.

Abdullah Mansoor, Malgorzata Chrzanowska-Jeske

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2022

RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing.

Abdullah Mansoor, Malgorzata Chrzanowska-Jeske

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Fast Buffer Count Estimation in 3D IC Floorplanning.

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fast Thermal Goodness Evaluation of a 3D-IC Floorplan.

Satya K. Vendra, Malgorzata Chrzanowska-Jeske

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2019

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile.

Satya K. Vendra, Malgorzata Chrzanowska-Jeske

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Tutorial 2A: 3D integration - challenges and advantages.

Malgorzata Chrzanowska-Jeske, Jürgen Becker

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Performance optimization and power efficiency in 3D IC with buffer insertion scheme.

Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Buffered Interconnects in 3D IC Layout Design.

Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

2015

Dynamic nets-to-TSVs assignment in 3D floorplanning.

Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

TSVs in early layout design exploration for 3D ICs.

Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Delay and power optimization with TSV-aware 3D floorplanning.

Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes.

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

3D floorplanning with nets-to-TSVs assignment.

Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Fast floorplanning with placement constraints.

Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Just because we teach it does not mean they use it: Case of programming skills.

Branimir Pejcinovic, Melinda Holtzman, Malgorzata Chrzanowska-Jeske, Phillip K. Wong

Proceedings of the IEEE Frontiers in Education Conference, 2013

TSV capacitance aware 3-D floorplanning.

Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Performance analysis of CNFET based circuits in the presence of fabrication imperfections.

Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

TSV stress-aware performance and reliability analysis.

Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Fast floorplanning for fixed-outline and nonrectangular regions.

Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs.

Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.

Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Yield improvement of 3D ICs in the presence of defects in through signal vias.

Rajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Yield enhancement by tube redundancy in CNFET-based circuits.

Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Placement-aware 3D Floorplanning.

Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Optimization of active circuits for substrate noise suppression.

Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Carbon nanotube circuit design choices in the presence of metallic tubes.

Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Rectangular 3D wirelength distribution models.

Rajeev K. Nain, Rajarshi Ray, Malgorzata Chrzanowska-Jeske

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

A novel net-degree distribution model and its application to floorplanning benchmark generation.

Tao Wan, Malgorzata Chrzanowska-Jeske

Integr., 2007

Supply current spectrum estimation of digital cores at early design.

Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske

IET Circuits Devices Syst., 2007

2006

Linear cofactor relationships in Boolean functions.

Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Using simulation and satisfiability to compute flexibilities in Boolean networks.

Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Estimation of supply current spectrum for early noise evaluation.

Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.

Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske

Proceedings of the 43rd Design Automation Conference, 2006

2005

Synthesis for regularity using decision diagrams [logic IC synthesis and layout].

Malgorzata Chrzanowska-Jeske, Alan Mishchenko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Modeling of substrate noise block properties for early prediction.

Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Considering layout for test scheduling of core-based SoCs.

Yu Xia, Malgorzata Chrzanowska-Jeske

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Detecting support-reducing bound sets using two-cofactor symmetries.

Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Substrate noise modeling in early floorplanning of MS-SOCs.

Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Substrate noise optimization in early floorplanning for mixed signal SOCs.

Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Prediction of interconnect net-degree distribution based on Rent's rule.

Tao Wan, Malgorzata Chrzanowska-Jeske

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Generating random benchmark circuits for floorplanning.

Tao Wan, Malgorzata Chrzanowska-Jeske

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Substrate noise-aware floorplanning for mixed-signal SOCs.

Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Board-level multiterminal net assignment for the partial cross-bar architecture.

Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola

IEEE Trans. Very Large Scale Integr. Syst., 2003

Integrated floorplanning with buffer/channel insertion for bus-based designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Graph-based approach to evaluate net routability of a floorplan.

Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Floorplanning with performance-based clustering.

Malgorzata Chrzanowska-Jeske, Benyi Wang, Garrison W. Greenwood

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.

Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Core-based SoC test scheduling using evolutionary algorithm.

Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang

Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts.

Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler

VLSI Design, 2002

Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs.

Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski

VLSI Design, 2002

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani

Proceedings of 2002 International Symposium on Physical Design, 2002

ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules.

Benyi Wang, Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Board-level multiterminal net assignment.

Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules.

Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood, Benyi Wang

Proceedings of the 2002 Congress on Evolutionary Computation, 2002

2001

A global approach to the variable ordering problem in PSBDDs.

Wei Wang, Malgorzata Chrzanowska-Jeske

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Generalized symmetric variables.

Malgorzata Chrzanowska-Jeske

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Regular Realization of Symmetric Functions Using Reversible Logic.

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

2000

Disjunctive Decomposition of Switching Functions Using Symmetry Information.

Malgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

1999

Logic Synthesis for a Regular Layout.

Malgorzata Chrzanowska-Jeske, Yang Xu, Marek A. Perkowski

VLSI Design, 1999

Regular symmetric arrays for non-symmetric functions.

Malgorzata Chrzanowska-Jeske

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Generalized symmetric and generalized pseudo-symmetric functions.

Malgorzata Chrzanowska-Jeske

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Variable ordering for regular layout representation.

Malgorzata Chrzanowska-Jeske, Yang Xu

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996

Synthesis approach to multi-level regular representation for combinational circuits.

Malgorzata Chrzanowska-Jeske, Chungping Guo

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

A New Design Methodology for Two-Dimensional Logic Arrays.

Ning Song, Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi

VLSI Design, 1995

Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions.

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi, Ingo Schäfer

VLSI Design, 1995

Tree restructuring approach to mapping problem in cellular-architecture FPGAs.

Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi

Proceedings of the Proceedings EURO-DAC'95, 1995

Layout synthesis for datapath designs.

Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

An Exact Solution to the Fitting Problem in the Application Specific State Machine Device.

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Edmund Pierzchala, Alan J. Coppola

J. Circuits Syst. Comput., 1994

Multiple-Valued-Input TANT Networks.

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Output Column Folding for Cellular-Architecture FPGAs.

Ning Song, Malgorzata Chrzanowska-Jeske

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.

Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski

Proceedings of the 31st Conference on Design Automation, 1994

1993

An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.

Malgorzata Chrzanowska-Jeske, Steffen Goller, Ingo Schäfer

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device.

Malgorzata Chrzanowska-Jeske, Steffen Goller

Proceedings of the European Design Automation Conference 1993, 1993

1990

Minimization of multioutput TANT networks for unlimited fan-in network model.

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990