Malay K. Ganai

According to our database1, Malay K. Ganai authored at least 62 papers between 1999 and 2014.

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Bibliography

2014
Environment-Sensitive Performance Tuning for Distributed Service Orchestration.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2014 - 11th International Conference, Eugene, OR, USA, June 30, 2014

ReproLite: A Lightweight Tool to Quickly Reproduce Hard System Bugs.
Proceedings of the ACM Symposium on Cloud Computing, 2014

2013
SETSUDŌ: perturbation-based testing framework for scalable distributed systems.
Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems, 2013

Efficient data race prediction with incremental reasoning on time-stamped lock history.
Proceedings of the 2013 28th IEEE/ACM International Conference on Automated Software Engineering, 2013

2012
DTAM: dynamic taint analysis of multi-threaded programs for relevancy.
Proceedings of the 20th ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE-20), 2012

Dynamic Livelock Analysis of Multi-threaded Programs.
Proceedings of the Runtime Verification, Third International Conference, 2012

2011
Symbolic predictive analysis for concurrent programs.
Formal Aspects Comput., 2011

Predicting Concurrency Failures in the Generalized Execution Traces of x86 Executables.
Proceedings of the Runtime Verification - Second International Conference, 2011

BEST: A symbolic testing tool for predicting multi-threaded program failures.
Proceedings of the 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011

Scalable and precise symbolic analysis for atomicity violations.
Proceedings of the 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011

2010
Trace-Based Symbolic Analysis for Atomicity Violations.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2010

Interval Analysis for Concurrent Trace Programs Using Transaction Sequence Graphs.
Proceedings of the Runtime Verification - First International Conference, 2010

Numerical stability analysis of floating-point computations using software model checking.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Efficient state space exploration: Interleaving stateless and state-based model checking.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Propelling SAT and SAT-based BMC using careset.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Scalable and precise program analysis at NEC.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Contessa: Concurrency Testing Augmented with Symbolic Analysis.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
Reduction of Verification Conditions for Concurrent System Using Mutually Atomic Transactions.
Proceedings of the Model Checking Software, 2009

Bang for the buck: Improvising and scheduling verification engines for effective resource utilization.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

Efficient decision procedure for non-linear arithmetic constraints using CORDIC.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Symbolic Predictive Analysis for Concurrent Programs.
Proceedings of the FM 2009: Formal Methods, 2009

2008
Efficient SAT-based bounded model checking for software verification.
Theor. Comput. Sci., 2008

Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Efficient Modeling of Concurrent Systems in BMC.
Proceedings of the Model Checking Software, 2008

PED: Proof-Guided Error Diagnosis by Triangulation of Program Error Causes.
Proceedings of the Sixth IEEE International Conference on Software Engineering and Formal Methods, 2008

Embedded software verification: challenges and solutions.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework.
Proceedings of the Hardware and Software: Verification and Testing, 2008

Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT().
Proceedings of the Hardware and Software: Verification and Testing, 2008

Completeness in SMT-based BMC for Software Programs.
Proceedings of the Design, Automation and Test in Europe, 2008

Partial order reduction for scalable testing of systemC TLM designs.
Proceedings of the 45th Design Automation Conference, 2008

Tunneling and slicing: towards scalable BMC.
Proceedings of the 45th Design Automation Conference, 2008

2007
SAT-Based Scalable Formal Verification Solutions
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-69167-1, 2007

SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic.
J. Satisf. Boolean Model. Comput., 2007

Synthesizing "Verification Aware" Models: Why and How?
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Efficient BMC for Multi-Clock Systems with Clocked Specifications.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Efficient distributed SAT and SAT-based distributed Bounded Model Checking.
Int. J. Softw. Tools Technol. Transf., 2006

<i>SDSAT</i>: Tight Integration of <i>Small Domain Encoding</i> and <i>Lazy</i> Approaches in a Separation Logic Solver.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2006

SAT-Based Verification Methods and Applications in Hardware Verification.
Proceedings of the Formal Methods for Hardware Verification, 2006

Accelerating high-level bounded model checking.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Predicate learning and selective theory deduction for a difference logic solver.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Localization and Register Sharing for Predicate Abstraction.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

<i>DiVer</i>: SAT-Based Model Checking Platform for Verifying Large Scale Systems.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination.
Proceedings of the Logic for Programming, 2005

Model Checking C Programs Using F-SOFT.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Verification of Embedded Memory Systems using Efficient Memory Modeling.
Proceedings of the 2005 Design, 2005

Beyond safety: customized SAT-based model checking.
Proceedings of the 42nd Design Automation Conference, 2005

F-Soft: Software Verification Platform.
Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2004
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient Modeling of Embedded Memories in Bounded Model Checking.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003
Iterative Abstraction using SAT-based BMC with Proof Analysis.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Learning from BDDs in SAT-based bounded model checking.
Proceedings of the 40th Design Automation Conference, 2003

Abstraction and BDDs Complement SAT-Based BMC in DiVer.
Proceedings of the Computer Aided Verification, 15th International Conference, 2003

2002
Robust Boolean reasoning for equivalence checking and functional property verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Improved SAT-Based Bounded Reachability Analysis.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.
Proceedings of the 39th Design Automation Conference, 2002

2001
SIVA: A System for Coverage-Directed State Space Search.
J. Electron. Test., 2001

Rarity based guided state space search.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Circuit-based Boolean Reasoning.
Proceedings of the 38th Design Automation Conference, 2001

1999
Performance Driven Synthesis for Pass-Transistor Logic.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Enhancing Simulation with BDDs and ATPG.
Proceedings of the 36th Conference on Design Automation, 1999


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