Makoto Saen

According to our database1, Makoto Saen authored at least 9 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2017
Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA.
IEICE Trans. Electron., 2017

2012
Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors.
Proceedings of the 2012 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2012

2010
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
IEEE J. Solid State Circuits, 2010

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
IEEE J. Solid State Circuits, 2010

Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2007
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
Elastic shared resource scheduling SOC interconnect architecture for real-time system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004


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