Makarand Shirasgaonkar

According to our database, Makarand Shirasgaonkar authored at least 4 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.

Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble

IEEE J. Solid State Circuits, 2015

2014

An Adaptive Body-Biased Clock Generation System in 28nm CMOS.

Makarand Shirasgaonkar, Roxanne Vu, Deborah Dressler, Nhat Nguyen, Kambiz Kaviani, Yueyong Wang

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.

Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble

Proceedings of the Symposium on VLSI Circuits, 2014

2012

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.

Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012