Majid Sarrafzadeh

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Dynamic reconfiguration in sensor networks with regenerative energy sources.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

The Development of an In-Vivo Active Pressure Monitoring System.

[BibT_eX]

[DOI]

Proceedings of the 4th International Workshop on Wearable and Implantable Body Sensor Networks, 2007

Delay aware, reconfigurable security for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2nd International ICST Conference on Body Area Networks, 2007

Lightweight medical BodyNets.

[BibT_eX]

[DOI]

Proceedings of the 2nd International ICST Conference on Body Area Networks, 2007

Congestion Minimization in Modern Placement Circuits.

[BibT_eX]

[DOI]

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

Adaptive Electrocardiogram Feature Extraction on Distributed Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2006

A Unified Theory of Timing Budget Management.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Optimal register sharing for high-level synthesis of SSA form programs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

General Delay Budgeting on Directed Acyclic Graphs with Applications in CAD.

[BibT_eX]

[DOI]

Electron. Notes Discret. Math., 2006

Adaptive Medical Feature Extraction for Resource Constrained Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE Conference on Pervasive Computing and Communications Workshops (PerCom 2006 Workshops), 2006

Dragon2006: blockage-aware congestion-controlling mixed-size placer.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Physical Design, 2006

Low power light-weight embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Routing algorithms: architecture driven rerouting enhancement for FPGAs.

[BibT_eX]

[DOI]

Taraneh Taghavi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Energy Minimization and Reliability for Wearable Medical Applications.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

Layout driven data communication optimization for high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

The Design of a Decentralized Electronic Triage System.

[BibT_eX]

[DOI]

Proceedings of the AMIA 2006, 2006

2005

A scheduling algorithm for optimization and early planning in high-level synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

On effective slack management in postscheduling phase.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Epsilon-Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems.

[BibT_eX]

[DOI]

Roozbeh Jafari

J. Low Power Electron., 2005

Reconfiguration in network of embedded systems: Challenges and adaptive tracking case study.

[BibT_eX]

[DOI]

J. Embed. Comput., 2005

Efficient placement and routing in grid-based networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Adaptive and fault tolerant medical vest for life-critical medical monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

An Efficient Placement and Routing Technique for Fault-Tolerant Distributed Embedded Computing.

[BibT_eX]

[DOI]

Roozbeh Jafari

Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Wireless Sensor Networks for Health Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2nd Annual International Conference on Mobile and Ubiquitous Systems (MobiQuitous 2005), 2005

A dictionary construction technique for code compression systems with echo instructions.

[BibT_eX]

[DOI]

Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

Quick Reconfiguration in Clustered Micro-Sequencer.

[BibT_eX]

[DOI]

Roozbeh Jafari

Seda Ogrenci Memik

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Routing algorithms: enhancing routability & enabling ECO (abstract only).

[BibT_eX]

[DOI]

Taraneh Taghavi

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Timing driven gate duplication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Collaborative and Reconfigurable Object Tracking.

[BibT_eX]

[DOI]

J. Supercomput., 2004

An optimal algorithm for minimizing run-time reconfiguration delay.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Optimal integer delay-budget assignment on directed acyclic graphs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

Instruction Selection for Compilers that Target Architectures with Echo Instructions.

[BibT_eX]

[DOI]

Philip Brisk

Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Transistor Level Budgeting for Power Optimization.

[BibT_eX]

[DOI]

Eren Kursun

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Innovate or perish: FPGA physical design.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

Routing resources consumption on M-arch and X-arch.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A unified theory of timing budget management.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Incremental Timing Budget Management in Programmable Systems.

[BibT_eX]

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.

[BibT_eX]

[DOI]

Philip Brisk

Adam Kaplan

Proceedings of the 41th Design Automation Conference, 2004

2003

Congestion reduction during placement with provably good approximation bound.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Routability-driven white space allocation for fixed-die standard-cell placement.

[BibT_eX]

[DOI]

Bo-Kyung Choi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Creating and exploiting flexibility in rectilinear Steiner trees.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analysis and FPGA Implementation of Image Restoration under Resource Constraints.

[BibT_eX]

[DOI]

Seda Ogrenci Memik

IEEE Trans. Computers, 2003

Flow-Based Cell Moving Algorithm for Desired Cell Distribution.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Trade-off Oriented Placement Tool.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Achieving Design Closure Through Delay Relaxation Parameter.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On computation and resource management in an FPGA-based computation environment.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Customized regular channel design in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Improving Performance and Quality thru Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study.

[BibT_eX]

Hyun J. Moon

Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003

Collaborative and Reconfigurable Object Tracking.

[BibT_eX]

Hyun J. Moon

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

Optimal integer delay budgeting on directed acyclic graphs.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Optimal reconfiguration sequence management.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Guest editorial.

[BibT_eX]

[DOI]

Rajeev Jayaraman

ACM Trans. Design Autom. Electr. Syst., 2002

Congestion estimation during top-down placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Pattern routing: use and theory for increasing predictability andavoiding coupling.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Predicting potential performance for digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Predictability in RT-Level Designs.

[BibT_eX]

[DOI]

Eren Kursun

J. Circuits Syst. Comput., 2002

Budget Management with Applications.

[BibT_eX]

[DOI]

Algorithmica, 2002

On the Sensitivity of Incremental Algorithms for Combinatorial Auctions.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE International Workshop on Advanced Issues of E-Commerce and Web-Based Information Systems (WECWIS'02), 2002

Predictability: Definition, Analysis and Optimization.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Early evaluation techniques for low power binding.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Activity-sensitive clock tree construction for low power.

[BibT_eX]

[DOI]

Changjun Kang

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Standard-Cell Placement Tool for Designs with High Row Utilization.

[BibT_eX]

[DOI]

Bo-Kyung Choi

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Timing-driven placement using design hierarchy guided constraint generation.

[BibT_eX]

[DOI]

Bo-Kyung Choi

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Predictability: definition, ananlysis and optimization.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A general framework for tracking objects in a multi-camera environment.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Digital and Computational Video, 2002

Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Instruction generation and regularity extraction for reconfigurable processors.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2002

2001

Power Optimization of Delay Constrained Circuits.

[BibT_eX]

[DOI]

VLSI Design, 2001

Fast floorplanning for effective prediction and construction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

On gate level power optimization using dual-supply voltages.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

On the complexity of gate duplication.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Activity-driven clock design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Wirelength estimation based on rent exponents of partitioning and placement.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Design and analysis of physical design algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Differences in ASIC, COT and processor design (panel).

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

An exact algorithm for coupling-free routing.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Congestion Reduction During Placement Based on Integer Programming.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A Super-Scheduler for Embedded Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Instruction Generation for Hybrid Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Layout aware retiming.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

A Quick Safari Through the Reconfiguration Jungle.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Creating and Exploiting Flexibility in Steiner Trees.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Seda Ogrenci

Proceedings of the 38th Design Automation Conference, 2001

Timing driven gate duplication in technology independent phase.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

RPack: routability-driven packing for cluster-based FPGAs.

[BibT_eX]

[DOI]

Seda Ogrenci Memik

Proceedings of ASP-DAC 2001, 2001

2000

Congestion minimization during placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Fundamental CAD algorithms.

[BibT_eX]

[DOI]

Melvin A. Breuer

Fabio Somenzi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On the Power of Logic Resynthesis.

[BibT_eX]

[DOI]

SIAM J. Comput., 2000

An application of dynamic programming to crew balancing at Burlington Northern Santa Fe Railway.

[BibT_eX]

[DOI]

Michael F. Gorman

Int. J. Serv. Technol. Manag., 2000

Fast Template Placement for Reconfigurable Computing Systems.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2000

Quality of EDA CAD Tools: Definitions, Metrics and Directions.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A snap-on placement tool.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Multi-center congestion estimation and minimization during placement.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Incremental physical design.

[BibT_eX]

[DOI]

Jason Cong

Proceedings of the 2000 International Symposium on Physical Design, 2000

Fast Hierarchical Floorplanning with Congestion and Timing Control.

[BibT_eX]

[DOI]

Abhishek Ranjan

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

DRAGON2000: Standard-Cell Placement Tool for Large Industry Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Timing Driven Gate Duplication: Complexity Issues and Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Predictable Routing.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Incremental CAD.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Potential Slack: An Effective Metric of Combinational Circuit Performance.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Fast and accurate estimation of floorplans in logic/high-level synthesis.

[BibT_eX]

[DOI]

Abhishek Ranjan

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

FPGA implementation and analysis of image restoration.

[BibT_eX]

[DOI]

F. S. Ogrenci

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

A C to Hardware/Software Compiler.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Modeling and minimization of routing congestion.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Multi-way partitioning using bi-partition heuristics.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

Power reduction by simultaneous voltage scaling and gate sizing.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Placement with Incomplete Data.

[BibT_eX]

[DOI]

Prithviraj Banerjee

VLSI Design, 1999

Evaluation and optimization of replication algorithms for logic bipartitioning.

[BibT_eX]

[DOI]

Morgan Enos

Scott Hauck

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Nostradamus: a floorplanner of uncertain designs.

[BibT_eX]

[DOI]

Samjung Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

On the Sum Coloring Problem on Interval Graphs.

[BibT_eX]

[DOI]

Sara Nicoloso

X. Song

Algorithmica, 1999

Two-Way and Multiway Partitioning of a Set of Intervals for Clique-Width Maximization.

[BibT_eX]

[DOI]

Algorithmica, 1999

Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

On the behavior of congestion minimization during placement.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

A fast algorithm for routability testing.

[BibT_eX]

[DOI]

Toshihiko Takahashi

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Scheduling with multiple voltages under resource constraints.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

Provably good algorithm for low power consumption with dual supply voltages.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

An Incremental Floorplanner.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Fast Online Placement for Reconfigurable Computing.

[BibT_eX]

[DOI]

Kiarash Barzagan

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

On Rectilinear Distance-Preserving Trees.

[BibT_eX]

[DOI]

VLSI Design, 1998

Exploiting Sleep Mode for Memory Partitioning and Other Applications.

[BibT_eX]

[DOI]

VLSI Design, 1998

Guest Editorial.

[BibT_eX]

[DOI]

Andrew B. Kahng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Four-bend top-down global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Floating Steiner Trees.

[BibT_eX]

[DOI]

C. K. Wong

IEEE Trans. Computers, 1998

Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1998

Partitioning sequential circuits for low power.

[BibT_eX]

[DOI]

Sumit Roy

Prithviraj Banerjee

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Nostradamus: a floorplanner of uncertain design.

[BibT_eX]

[DOI]

Samjung Kim

Proceedings of the 1998 International Symposium on Physical Design, 1998

Low Power Driven Scheduling and Binding.

[BibT_eX]

[DOI]

Jim E. Crenshaw

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Potential-NRG: Placement with Incomplete Data.

[BibT_eX]

[DOI]

Prithviraj Banerjee

Proceedings of the 35th Conference on Design Automation, 1998

1997

Minimal buffer insertion in clock trees with skew and slew rate constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

A delay budgeting algorithm ensuring maximum flexibility in placement.

[BibT_eX]

[DOI]

David A. Knol

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Scheduling with multiple voltages.

[BibT_eX]

[DOI]

Integr., 1997

NRG: global and detailed placement.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Replication for logic bipartitioning.

[BibT_eX]

[DOI]

Morgan Enos

Scott Hauck

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Accurate high level datapath power estimation.

[BibT_eX]

[DOI]

Jim E. Crenshaw

Proceedings of the European Design and Test Conference, 1997

Unification of Budgeting and Placement.

[BibT_eX]

[DOI]

David A. Knol

Proceedings of the 34st Conference on Design Automation, 1997

Cube-embedding based state encoding for low power design.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

State Encoding of Finite State Machines for Low Power Design.

[BibT_eX]

[DOI]

Gary K. H. Yeap

J. Circuits Syst. Comput., 1996

An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

A buffer distribution algorithm for high-performance clock net optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

Discrete Warehouse Problem.

[BibT_eX]

[DOI]

Malgorzata Marek-Sadowska

Sanjeev R. Maddila

Theor. Comput. Sci., 1995

The crossing distribution problem [IC layout].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Sliceable Floorplanning by Graph Dualization.

[BibT_eX]

[DOI]

Gary K. H. Yeap

SIAM J. Discret. Math., 1995

Variable voltage scheduling.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

A Linear Arrangement Problem with Applications.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Activity-driven clock design for low power circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

System partitioning to maximize sleep time.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Constrained Register Allocation in Bus Architectures.

[BibT_eX]

[DOI]

Elof Frank

Proceedings of the 32st Conference on Design Automation, 1995

Memory Segmentation to Exploit Sleep Mode Operation.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

On the Minimum Density Interconnection Tree Problem.

[BibT_eX]

[DOI]

VLSI Design, 1994

Single-layer global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Correction to "Boundary single-layer routing with movable terminals".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Complexity of the lookup-table minimization problem for FPGA technology mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

A weighted Steiner tree-based global router with simultaneous length and density minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Wiring Knock-Knee Layouts: A Global Approach.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1994

The pin redistribution problem in multi-chip modules.

[BibT_eX]

[DOI]

Math. Program., 1994

Restricted track assignment with applications.

[BibT_eX]

[DOI]

Int. J. Comput. Geom. Appl., 1994

New Approximation Results on Graph Matching and related Problems.

[BibT_eX]

[DOI]

Yoji Kajitani

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1994

Clock period constrained minimal buffer insertion in clock trees.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

The reproducing placement problem with applications.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

FPGA Technology Mapping for Power Minimization.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic, 1994

Approximation Algorithm on Multi-Way Maxcut Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Algorithms, 1994

1993

A unified approach to floorplan sizing and enumeration.

[BibT_eX]

[DOI]

Gary K. H. Yeap

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Utilization of vacant terminals for improved over-the-cell channel routing.

[BibT_eX]

[DOI]

Nancy D. Holmes

Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An exact algorithm for single-layer wire length minimization.

[BibT_eX]

[DOI]

Jan-Ming Ho

Atsushi Suzuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Floor-Planning by Graph Dualization: 2-Concave Rectilinear Modules.

[BibT_eX]

[DOI]

Kok-Hoo Yeap

SIAM J. Comput., 1993

An Optimal Algorithm for the Maximum Three-Chain Problem.

[BibT_eX]

[DOI]

SIAM J. Comput., 1993

Maximum independent set of a permutation graph in K tracks.

[BibT_eX]

[DOI]

Int. J. Comput. Geom. Appl., 1993

High-Performance MCM Routing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

Floorplanning by Graph Dualization: L-shaped Modules.

[BibT_eX]

[DOI]

Yachyang Sun

Algorithmica, 1993

Maximum k-Covering of Weighted Transitive Graphs with Applications.

[BibT_eX]

[DOI]

Algorithmica, 1993

GEM: A Geometric Algorithm for Scheduling.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimum Density Interconneciton Trees.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Transforming an arbitrary floorplan into a sliceable one.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

A Nuffer Distribution Algorithm for High-Speed Clock Routing.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Hierarchical Steiner tree construction in uniform orientations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Provably good performance-driven global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Bottleneck Steiner Trees in the Plane.

[BibT_eX]

[DOI]

C. K. Wong

IEEE Trans. Computers, 1992

An Optimal Algorithm for the Maximum Two-Chain Problem.

[BibT_eX]

[DOI]

SIAM J. Discret. Math., 1992

General Circular Permutation Layout.

[BibT_eX]

[DOI]

Math. Syst. Theory, 1992

Planar Routing around a Rectangle.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1992

Vlsi Architectures for Iterative Image Restoration.

[BibT_eX]

[DOI]

Srikanta P. R. Kumar

J. Circuits Syst. Comput., 1992

Circular Permutation Graph Family with Applications.

[BibT_eX]

[DOI]

Discret. Appl. Math., 1992

Wiring Knock-Knee Layouts: A Global Appoach.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Computation, Third International Symposium, 1992

Rstricted Track Assignment with Applications.

[BibT_eX]

[DOI]

Proceedings of the Algorithms and Computation, Third International Symposium, 1992

A wire-length minimization algorithm for single-layer layouts.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Over-the-Cell Routers for New Cell Model.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Over-the-Cell Channel Routing for High Performance Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Boundary single-layer routing with movable terminals.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Topological Via Minimization Revisited.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1991

Optimal VLSI architectures for multidimensional DFT (preliminary version).

[BibT_eX]

[DOI]

Gianfranco Bilardi

Scot W. Hornick

SIGARCH Comput. Archit. News, 1991

A Parallel Algorithm for Minimum Dual-Cover with Application to CMOS Layout.

[BibT_eX]

[DOI]

Y. M. Huang

J. Circuits Syst. Comput., 1991

Tree placement in Cascode-Switch macros.

[BibT_eX]

[DOI]

Integr., 1991

An optimal algorithm for rectilinear steiner trees for channels with obstacles.

[BibT_eX]

[DOI]

C. K. Wong

Int. J. Circuit Theory Appl., 1991

Maximum Independent Set of a Permutation Graph in <i>k</i> Tracks.

[BibT_eX]

[DOI]

Malgorzata Marek-Sadowska

Proceedings of the ISA '91 Algorithms, 1991

Performance-Driven Global Routing for Cell Based ICs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

The Crossing Distribution Problem.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Algorithms for Three-Layer Over-The-Cell Channel Routing.

[BibT_eX]

[DOI]

Nancy D. Holmes

Naveed A. Sherwani

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals.

[BibT_eX]

[DOI]

Nancy D. Holmes

Naveed A. Sherwani

Proceedings of the 28th Design Automation Conference, 1991

1990

Layer assignment for multichip modules.

[BibT_eX]

[DOI]

Jan-Ming Ho

Gopalakrishnan Vijayan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Pad minimization for planar routing of multiple power nets.

[BibT_eX]

[DOI]

Jan-Ming Ho

Gopalakrishnan Vijayan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Global routing based on Steiner min-max trees.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Area Minimization in a Three-Sided Switchbox by Sliding the Modules.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

Stretching a Knock-Knee Layout for Multilayer Wiring.

[BibT_eX]

[DOI]

Martin L. Brady

IEEE Trans. Computers, 1990

Minimum Cuts for Circular-Arc Graphs.

[BibT_eX]

[DOI]

Ying-Fung Wu

SIAM J. Comput., 1990

Optimal gate-matrix layout of CMOS functional cells.

[BibT_eX]

[DOI]

C. C. Su

Integr., 1990

Planar subset of multi-terminal nets.

[BibT_eX]

[DOI]

Integr., 1990

Vertex-Disjoint Trees and Boundary Single-Layer Routing.

[BibT_eX]

[DOI]

Proceedings of the Graph-Theoretic Concepts in Computer Science, 1990

A Parallel Algorithm for Two-Layer Wirin.

[BibT_eX]

Manbir Nag

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1989

A new approach to topological via minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Optimal VLSI Architectures for Multidimensional DFT.

[BibT_eX]

[DOI]

Gianfranco Bilardi

Scot W. Hornick

Proceedings of the ACM Symposium on Parallel Algorithms and Architectures, 1989

A powerful global router: based on Steiner min-max trees.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Parallel processing architectures for iterative image restoration.

[BibT_eX]

[DOI]

Srikanta P. R. Kumar

Proceedings of the IEEE International Conference on Acoustics, 1989

1987

Hierarchical Approaches to Vlsi Circuit Layout

[BibT_eX]

[DOI]

PhD thesis, 1987

Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A bottom-up layout technique based on two-rectangle routing.

[BibT_eX]

[DOI]

Franco P. Preparata

Integr., 1987

On Problem Transformability in VLSI.

[BibT_eX]

[DOI]

Scot W. Hornick

Algorithmica, 1987

1986

Channel Routing in Knock-Knee Mode: Simplified Algorithms and Proofs.

[BibT_eX]

[DOI]

Kurt Mehlhorn

Franco P. Preparata