Majid Jalalifar
Orcid: 0000-0001-5478-6748
According to our database1,
Majid Jalalifar
authored at least 7 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2023
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2018
A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2016
A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2008
A novel topology in reversed nested miller compensation using dual-active capacitance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008