Majid Amini Valashani
Orcid: 0000-0001-8890-6496
According to our database1,
Majid Amini Valashani
authored at least 5 papers
between 2016 and 2022.
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Bibliography
2022
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process.
Integr., 2022
2021
An input controlled leakage restrainer transistor-based technique for leakage and short-circuit power reduction of 1-bit hybrid full adders.
Int. J. Circuit Theory Appl., 2021
A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology.
Circuits Syst. Signal Process., 2021
2018
Microelectron. J., 2018
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016