Majed Valad Beigi
Orcid: 0000-0002-7701-7746Affiliations:
- Northwestern University, Department of Electrical Engineering and Computer Science
- Shahid Beheshti University, Faculty of Electrical and Computer Engineering
According to our database1,
Majed Valad Beigi
authored at least 19 papers
between 2012 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on dl.acm.org
On csauthors.net:
Bibliography
2024
2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
Reliability, Availability, and Serviceability Challenges for Heterogeneous System Design.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2020
DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2019
ACM Trans. Design Autom. Electr. Syst., 2019
2018
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2014
MIN: a power efficient mechanism to mitigate the impact of process variations on nanophotonic networks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2013
A Probabilistic Approach to Analysis of Reliability in n-D Meshes with Interconnect Router Failures
CoRR, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
PDR: A protocol for dynamic network reconfiguration based on deadlock recovery scheme.
Simul. Model. Pract. Theory, 2012
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip.
Microprocess. Microsystems, 2012
DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme
CoRR, 2012