Máire O'Neill

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

An Efficient and Parallel R-LWE Cryptoprocessor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Fast DRAM PUFs on Commodity Devices.

[BibT_eX]

[DOI]

Jack Miskelly

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

High Performance Modular Multiplication for SIDH.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

Ten years of hardware Trojans: a survey from the attacker's perspective.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2020

A Novel Feature Extraction Strategy for Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Programmable Ring Oscillator PUF Based on Switch Matrix.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Security Analysis of Hardware Trojans on Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Secure Algorithm for Rounded Gaussian Sampling.

[BibT_eX]

[DOI]

Proceedings of the Cryptology and Network Security - 19th International Conference, 2020

2019

Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

BEARZ Attack FALCON: Implementation Attacks with Countermeasures on the FALCON signature scheme.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Lattice-based Cryptography for IoT in A Quantum World: Are We Ready?

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

An Improved Automatic Hardware Trojan Generation Platform.

[BibT_eX]

[DOI]

Shichao Yu

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Multi-Incentive Delay-Based (MID) PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018

Data Compression Device Based on Modified LZ4 Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2018

On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.

[BibT_eX]

[DOI]

IEEE Access, 2018

Addressing Side-Channel Vulnerabilities in the Discrete Ziggurat Sampler.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Design of Majority Logic (ML) Based Approximate Full Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Optimization of Modular Multiplication for SIDH.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Modelling Attack Analysis of Configurable Ring Oscillator (CRO) PUF Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Physical Protection of Lattice-Based Cryptography: Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A machine learning attack resistant multi-PUF design on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Approximate Computing and Its Application to Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the Cyber-Physical Systems Security., 2018

2017

Improved Reliability of FPGA-Based PUF Identification Generator Design.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2017

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Evaluation of Large Integer Multiplication Methods on Hardware.

[BibT_eX]

[DOI]

Ciara Rafferty

IEEE Trans. Computers, 2017

GLITCH: A Discrete Gaussian Testing Suite For Lattice-Based Cryptography.

[BibT_eX]

[DOI]

James Howe

IACR Cryptol. ePrint Arch., 2017

XOR gate based low-cost configurable RO PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Compact and provably secure lattice-based signatures in hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA-based strong PUF with increased uniqueness and entropy properties.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies.

[BibT_eX]

[DOI]

John McAllister

Maxime Pelcat

J. Signal Process. Syst., 2016

Design and Analysis of Inexact Floating-Point Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Novel lightweight FF-APUF design for FPGA.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Lattice-based cryptography: From reconfigurable hardware to ASIC.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: An automatic evaluation platform for physical unclonable function test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Time-independent discrete Gaussian sampling for post-quantum cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Standard lattices in hardware.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Secure architectures of future emerging cryptography <i>SAFEcrypto</i>.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015

Introduction for Embedded Platforms for Cryptography in the Coming Decade.

[BibT_eX]

[DOI]

Patrick Schaumont

Tim Güneysu

ACM Trans. Embed. Comput. Syst., 2015

Practical Lattice-Based Digital Signature Schemes.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2015

Privacy region protection for H.264/AVC with enhanced scrambling effect and a low bitrate overhead.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2015

Improving RO PUF design using frequency distribution characteristics.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Security Analysis on RFID Mutual Authentication Protocol.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications - 16th International Workshop, 2015

An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications - 16th International Workshop, 2015

RO PUF design in FPGAs with new comparison strategies.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Pre-processing power traces to defeat random clocking countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Ultra-compact and robust FPGA-based PUF identification generator.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Neural network based attack on a masked implementation of AES.

[BibT_eX]

[DOI]

Richard Gilmore

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On the Security of Balanced Encoding Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2015

2014

Security Issues in QCA Circuit Design - Power Analysis Attacks.

[BibT_eX]

[DOI]

Saket Srivastava

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Can leakage models be more efficient? non-linear models in side channel attacks.

[BibT_eX]

[DOI]

Qizhi Tian

Proceedings of the 2014 IEEE International Workshop on Information Forensics and Security, 2014

Accelerating integer-based fully homomorphic encryption using Comba multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Empirical evaluation of multi-device profiling side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Practical homomorphic encryption: A survey.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A unique and robust single slice FPGA identification generator.

[BibT_eX]

[DOI]

Julian P. Murphy

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-Speed Fully Homomorphic Encryption Over the Integers.

[BibT_eX]

[DOI]

Proceedings of the Financial Cryptography and Data Security, 2014

New FMO type to flag ROI in H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the 5th European Workshop on Visual Information Processing, 2014

2013

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2013

QCA Systolic Array Design.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Partial encryption by randomized zig-zag scanning for video encoding.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power analysis attack of QCA circuits: A case study of the Serpent cipher.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Privacy region protection for H.264/AVC by encrypting the intra prediction modes without drift error in I frames.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2013

Pre-processing power traces with a phase-sensitive detector.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE.

[BibT_eX]

[DOI]

Proceedings of the Financial Cryptography and Data Security, 2013

A tunable selective encryption scheme for H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the European Workshop on Visual Information Processing, 2013

2012

A novel common control channel security framework for cognitive radio networks.

[BibT_eX]

[DOI]

Int. J. Auton. Adapt. Commun. Syst., 2012

Self-Timed Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on New Technologies, 2012

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Adaptive binary mask for privacy region protection.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Cost-efficient decimal adder design in Quantum-dot cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Application-oriented SHA-256 hardware design for low-cost RFID.

[BibT_eX]

[DOI]

Xiaolin Cao

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

The improved sign bit encryption of motion vectors for H.264/AVC.

[BibT_eX]

[DOI]

Proceedings of the 20th European Signal Processing Conference, 2012

A review of QCA adders and metrics.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

Variable window power spectral density attack.

[BibT_eX]

[DOI]

Keanhong Boey

Proceedings of the 2011 IEEE International Workshop on Information Forensics and Security, 2011

A Private and Scalable Authentication for RFID Systems Using Reasonable Storage.

[BibT_eX]

[DOI]

Xiaolin Cao

Proceedings of the IEEE 10th International Conference on Trust, 2011

A Forward Private Protocol based on PRNG and LPN for Low-cost RFID .

[BibT_eX]

Xiaolin Cao

Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011

How Resistant are Sboxes to Power Analysis Attacks?

[BibT_eX]

[DOI]

Keanhong Boey

Roger F. Woods

Proceedings of the 4th IFIP International Conference on New Technologies, 2011

Design rules for Quantum-dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Power Spectral Density Side Channel Attack Overlapping Window Method.

[BibT_eX]

[DOI]

Keanhong Boey

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

Evaluation of Random Delay Insertion against DPA on FPGAs.

[BibT_eX]

[DOI]

Yingxi Lu

ACM Trans. Reconfigurable Technol. Syst., 2010

Low-cost digital signature architecture suitable for radio frequency identification tags.

[BibT_eX]

[DOI]

Matthew J. B. Robshaw

IET Comput. Digit. Tech., 2010

On Foundation and Construction of Physical Unclonable Functions.

[BibT_eX]

[DOI]

Jiang Wu

IACR Cryptol. ePrint Arch., 2010

A Hardware Wrapper for the SHA-3 Hash Algorithms.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2010

QCA Systolic Matrix Multiplier.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Differential Power Analysis of CAST-128.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Security of AES Sbox designs to power analysis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Lightweight DPA resistant solution on FPGA to counteract power models.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

FPGA Implementations of the Round Two SHA-3 Candidates.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

SEED masking implementations against power analysis attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Random clock against differential power analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Performance Analysis of Novel Randomly Shifted Certification Authority Authentication Protocol for MANETs.

[BibT_eX]

[DOI]

EURASIP J. Wirel. Commun. Netw., 2009

Common Control Channel Security Framework for Cognitive Radio Networks.

[BibT_eX]

[DOI]

Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

ASIC evaluation of ECHO hash function.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Is the differential frequency-based attack effective against random delay insertion?

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008

Differential Power Analysis of a SHACAL-2 hardware implementation.

[BibT_eX]

[DOI]

Yingxi Lu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

FPGA implementation and analysis of random delay insertion countermeasure against DPA.

[BibT_eX]

[DOI]

Yingxi Lu

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing.

[BibT_eX]

[DOI]

Nicolas Sklavos

Xinmiao Zhang

Mob. Networks Appl., 2007

Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks.

[BibT_eX]

Clare McGrath

Proceedings of the SECRYPT 2007, 2007

New Architectures for Low-Cost Public Key Cryptography on RFID Tags.

[BibT_eX]

[DOI]

Matthew J. B. Robshaw

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Exploring technology related design-space limitations of high performance network processing.

[BibT_eX]

[DOI]

Sakir Sezer

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Public Key Cryptography and RFID Tags.

[BibT_eX]

[DOI]

Matthew J. B. Robshaw

Proceedings of the Topics in Cryptology, 2007

2006

WLAN security processor.

[BibT_eX]

[DOI]

Neil Smyth

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Limitations of existing wireless networks authentication and key management techniques for MANETs.

[BibT_eX]

[DOI]

Clare McGrath

Proceedings of the International Symposium on Computer Networks, 2006

An Adaptable And Scalable Asymmetric Cryptographic Processor.

[BibT_eX]

[DOI]

Neil Smyth

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

High-Speed Hardware Architectures of the Whirlpool Hash Function.

[BibT_eX]

Aidan Savage

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

High-Radix Systolic Modular Multiplication on Reconfigurable Hardware.

[BibT_eX]

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor.

[BibT_eX]

[DOI]

P. Moore

Sakir Sezer

Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

2004

FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p).

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication.

[BibT_eX]

[DOI]