Máire O'Neill

Orcid: 0000-0002-6865-6212

Affiliations:
  • Queen's University Belfast, UK


According to our database1, Máire O'Neill authored at least 171 papers between 2001 and 2024.

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Bibliography

2024
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Quantum-Safe HIBE: Does It Cost a Latte?
IEEE Trans. Inf. Forensics Secur., 2024

Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Efficient Soft Core Multiplier for Post Quantum Digital Signatures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

FPGA Bitstream Fault Injection Attack and Countermeasures on the Sampling Counter in CRYSTALS Kyber.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Novel Methodology for Processor based PUF in Approximate Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining.
IEEE Trans. Computers, December, 2023

Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Towards a Lightweight CRYSTALS-Kyber in FPGAs: an Ultra-lightweight BRAM-free NTT Core.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A High-Performance SIKE Hardware Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Deep Learning-Based Hardware Trojan Detection With Block-Based Netlist Information Extraction.
IEEE Trans. Emerg. Top. Comput., 2022

A Dynamically Configurable PUF and Dynamic Matching Authentication Protocol.
IEEE Trans. Emerg. Top. Comput., 2022

Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs.
IEEE Trans. Emerg. Top. Comput., 2022

A High Performance SIKE Accelerator With High Frequency and Low Area-Time Product.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

AxRLWE: A Multilevel Approximate Ring-LWE Co-Processor for Lightweight IoT Applications.
IEEE Internet Things J., 2022

Efficient Pipelining Exploration for A High-performance CRYSTALS-Kyber Accelerator.
IACR Cryptol. ePrint Arch., 2022

Stacked Ensemble Model for Enhancing the DL based SCA.
Proceedings of the 19th International Conference on Security and Cryptography, 2022

Stacked Ensemble Models Evaluation on DL Based SCA.
Proceedings of the E-Business and Telecommunications - 19th International Conference, 2022

High Performance FPGA-based Post Quantum Cryptography Implementations.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

Better Security Estimates for Approximate, IoT-Friendly R-LWE Cryptosystems.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Security Vulnerabilities and Countermeasures for Approximate Circuits.
Proceedings of the Approximate Computing, 2022

2021
Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers.
IEEE Trans. Emerg. Top. Comput., 2021

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation.
IEEE Trans. Emerg. Top. Comput., 2021

A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices.
ACM J. Emerg. Technol. Comput. Syst., 2021

A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs.
J. Cryptogr. Eng., 2021

A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

High-Performance Systolic Array Montgomery Multiplier for SIKE.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Plaintext: A Missing Feature for Enhancing the Power of Deep Learning in Side-Channel Analysis? Breaking multiple layers of side-channel countermeasures.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

An Efficient and Parallel R-LWE Cryptoprocessor.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3.
IEEE Trans. Circuits Syst., 2020

Fast DRAM PUFs on Commodity Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

High Performance Modular Multiplication for SIDH.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities.
Proc. IEEE, 2020

Ten years of hardware Trojans: a survey from the attacker's perspective.
IET Comput. Digit. Tech., 2020

A Novel Feature Extraction Strategy for Hardware Trojan Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

AxMM: Area and Power Efficient Approximate Modular Multiplier for R-LWE Cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Programmable Ring Oscillator PUF Based on Switch Matrix.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Security Analysis of Hardware Trojans on Approximate Circuits.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

A Secure Algorithm for Rounded Gaussian Sampling.
Proceedings of the Cryptology and Network Security - 19th International Conference, 2020

2019
Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2019

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security.
ACM Trans. Embed. Comput. Syst., 2019

Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman.
IEEE Trans. Computers, 2019

A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations.
IEEE Trans. Computers, 2019

BEARZ Attack FALCON: Implementation Attacks with Countermeasures on the FALCON signature scheme.
IACR Cryptol. ePrint Arch., 2019

Lattice-based Cryptography for IoT in A Quantum World: Are We Ready?
IACR Cryptol. ePrint Arch., 2019

An Improved Automatic Hardware Trojan Generation Platform.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Multi-Incentive Delay-Based (MID) PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Theoretical Analysis of Delay-Based PUFs and Design Strategies for Improvement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

A Modeling Attack Resistant Deception Technique for Securing PUF based Authentication.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Data Compression Device Based on Modified LZ4 Algorithm.
IEEE Trans. Consumer Electron., 2018

On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography.
IEEE Trans. Computers, 2018

Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography.
IACR Cryptol. ePrint Arch., 2018

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design.
IEEE Access, 2018

Addressing Side-Channel Vulnerabilities in the Discrete Ziggurat Sampler.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Design of Majority Logic (ML) Based Approximate Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design and Optimization of Modular Multiplication for SIDH.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Modelling Attack Analysis of Configurable Ring Oscillator (CRO) PUF Designs.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Physical Protection of Lattice-Based Cryptography: Challenges and Solutions.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A machine learning attack resistant multi-PUF design on FPGA.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Attacking Arbiter PUFs Using Various Modeling Attack Algorithms: A Comparative Study.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Approximate Computing and Its Application to Hardware Security.
Proceedings of the Cyber-Physical Systems Security., 2018

2017
Improved Reliability of FPGA-Based PUF Identification Generator Design.
ACM Trans. Reconfigurable Technol. Syst., 2017

Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing.
IEEE Trans. Emerg. Top. Comput., 2017

Evaluation of Large Integer Multiplication Methods on Hardware.
IEEE Trans. Computers, 2017

GLITCH: A Discrete Gaussian Testing Suite For Lattice-Based Cryptography.
IACR Cryptol. ePrint Arch., 2017

XOR gate based low-cost configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Compact and provably secure lattice-based signatures in hardware.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA-based strong PUF with increased uniqueness and entropy properties.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies.
J. Signal Process. Syst., 2016

Design and Analysis of Inexact Floating-Point Adders.
IEEE Trans. Computers, 2016

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.
IEEE Trans. Computers, 2016

Novel lightweight FF-APUF design for FPGA.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Lattice-based cryptography: From reconfigurable hardware to ASIC.
Proceedings of the International Symposium on Integrated Circuits, 2016

Low-cost configurable ring oscillator PUF with improved uniqueness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Live demonstration: An automatic evaluation platform for physical unclonable function test.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Time-independent discrete Gaussian sampling for post-quantum cryptography.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Standard lattices in hardware.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Secure architectures of future emerging cryptography <i>SAFEcrypto</i>.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Introduction for Embedded Platforms for Cryptography in the Coming Decade.
ACM Trans. Embed. Comput. Syst., 2015

Practical Lattice-Based Digital Signature Schemes.
ACM Trans. Embed. Comput. Syst., 2015

Privacy region protection for H.264/AVC with enhanced scrambling effect and a low bitrate overhead.
Signal Process. Image Commun., 2015

Improving RO PUF design using frequency distribution characteristics.
IEICE Electron. Express, 2015

Security Analysis on RFID Mutual Authentication Protocol.
Proceedings of the Information Security Applications - 16th International Workshop, 2015

An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -.
Proceedings of the Information Security Applications - 16th International Workshop, 2015

RO PUF design in FPGAs with new comparison strategies.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Pre-processing power traces to defeat random clocking countermeasures.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Ultra-compact and robust FPGA-based PUF identification generator.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Neural network based attack on a masked implementation of AES.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

On the Security of Balanced Encoding Countermeasures.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Security Issues in QCA Circuit Design - Power Analysis Attacks.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Can leakage models be more efficient? non-linear models in side channel attacks.
Proceedings of the 2014 IEEE International Workshop on Information Forensics and Security, 2014

Accelerating integer-based fully homomorphic encryption using Comba multiplication.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Empirical evaluation of multi-device profiling side-channel attacks.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Practical homomorphic encryption: A survey.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A unique and robust single slice FPGA identification generator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-Speed Fully Homomorphic Encryption Over the Integers.
Proceedings of the Financial Cryptography and Data Security, 2014

New FMO type to flag ROI in H.264/AVC.
Proceedings of the 5th European Workshop on Visual Information Processing, 2014

2013
A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC.
IEEE Trans. Circuits Syst. Video Technol., 2013

QCA Systolic Array Design.
IEEE Trans. Computers, 2013

Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction.
IACR Cryptol. ePrint Arch., 2013

Partial encryption by randomized zig-zag scanning for video encoding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Power analysis attack of QCA circuits: A case study of the Serpent cipher.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Privacy region protection for H.264/AVC by encrypting the intra prediction modes without drift error in I frames.
Proceedings of the IEEE International Conference on Acoustics, 2013

Pre-processing power traces with a phase-sensitive detector.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE.
Proceedings of the Financial Cryptography and Data Security, 2013

A tunable selective encryption scheme for H.264/AVC.
Proceedings of the European Workshop on Visual Information Processing, 2013

2012
A novel common control channel security framework for cognitive radio networks.
Int. J. Auton. Adapt. Commun. Syst., 2012

Self-Timed Physically Unclonable Functions.
Proceedings of the 5th International Conference on New Technologies, 2012

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Adaptive binary mask for privacy region protection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Cost-efficient decimal adder design in Quantum-dot cellular automata.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Application-oriented SHA-256 hardware design for low-cost RFID.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

The improved sign bit encryption of motion vectors for H.264/AVC.
Proceedings of the 20th European Signal Processing Conference, 2012

A review of QCA adders and metrics.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Variable window power spectral density attack.
Proceedings of the 2011 IEEE International Workshop on Information Forensics and Security, 2011

A Private and Scalable Authentication for RFID Systems Using Reasonable Storage.
Proceedings of the IEEE 10th International Conference on Trust, 2011

A Forward Private Protocol based on PRNG and LPN for Low-cost RFID .
Proceedings of the SECRYPT 2011 - Proceedings of the International Conference on Security and Cryptography, Seville, Spain, 18, 2011

How Resistant are Sboxes to Power Analysis Attacks?
Proceedings of the 4th IFIP International Conference on New Technologies, 2011

Design rules for Quantum-dot Cellular Automata.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Power Spectral Density Side Channel Attack Overlapping Window Method.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Evaluation of Random Delay Insertion against DPA on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2010

Low-cost digital signature architecture suitable for radio frequency identification tags.
IET Comput. Digit. Tech., 2010

On Foundation and Construction of Physical Unclonable Functions.
IACR Cryptol. ePrint Arch., 2010

A Hardware Wrapper for the SHA-3 Hash Algorithms.
IACR Cryptol. ePrint Arch., 2010

QCA Systolic Matrix Multiplier.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Differential Power Analysis of CAST-128.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Security of AES Sbox designs to power analysis.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Lightweight DPA resistant solution on FPGA to counteract power models.
Proceedings of the International Conference on Field-Programmable Technology, 2010

FPGA Implementations of the Round Two SHA-3 Candidates.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

SEED masking implementations against power analysis attacks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Random clock against differential power analysis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Performance Analysis of Novel Randomly Shifted Certification Authority Authentication Protocol for MANETs.
EURASIP J. Wirel. Commun. Netw., 2009

Common Control Channel Security Framework for Cognitive Radio Networks.
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009

ASIC evaluation of ECHO hash function.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Is the differential frequency-based attack effective against random delay insertion?
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

2008
Differential Power Analysis of a SHACAL-2 hardware implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

FPGA implementation and analysis of random delay insertion countermeasure against DPA.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

2007
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function.
J. VLSI Signal Process., 2007

MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing.
Mob. Networks Appl., 2007

Identity Based Public Key Exchange (IDPKE) for Wireless Ad Hoc Networks.
Proceedings of the SECRYPT 2007, 2007

New Architectures for Low-Cost Public Key Cryptography on RFID Tags.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Exploring technology related design-space limitations of high performance network processing.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Public Key Cryptography and RFID Tags.
Proceedings of the Topics in Cryptology, 2007

2006
WLAN security processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Hardware Elliptic Curve Cryptographic Processor Over $\rm GF(p)$.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Limitations of existing wireless networks authentication and key management techniques for MANETs.
Proceedings of the International Symposium on Computer Networks, 2006

An Adaptable And Scalable Asymmetric Cryptographic Processor.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
High-Speed Hardware Architectures of the Whirlpool Hash Function.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

High-Radix Systolic Modular Multiplication on Reconfigurable Hardware.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor.
Proceedings of the Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 2005

2004
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p).
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

FPGA Montgomery Multiplier Architectures - A Comparison.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Rijndael FPGA Implementations Utilising Look-Up Tables.
J. VLSI Signal Process., 2003

A high-speed, low latency RSA decryption silicon core.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Very High Speed 17 Gbps SHACAL Encryption Architecture.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
Generic silicon architectures for encryption algorithm.
PhD thesis, 2002

Efficient single-chip implementation of SHA-384 and SHA-512.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.
Proceedings of the Field-Programmable Logic and Applications, 2001

High Performance Single-Chip FPGA Rijndael Algorithm Implementations.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2001


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