Mainak Chaudhuri
According to our database1,
Mainak Chaudhuri
authored at least 41 papers
between 2002 and 2024.
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Bibliography
2024
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
2021
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Shared Pattern History Tables in Multicomponent Branch Predictors With a Dealiasing Cache.
IEEE Embed. Syst. Lett., 2020
2019
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2017
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors.
ACM Trans. Embed. Comput. Syst., 2017
ACM Trans. Archit. Code Optim., 2017
Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
Proceedings of the 9th India Software Engineering Conference, 2016
Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors.
Proceedings of the 2016 International Conference on Supercomputing, 2016
2015
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2013
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Characterizing multi-threaded applications for designing sharing-aware last-level cache replacement policies.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013
2012
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
2010
Improving speculative loop parallelization via selective squash and speculation reuse.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Sci. Program., 2009
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
2007
IEEE Trans. Parallel Distributed Syst., 2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors.
Proceedings of the 2007 International Conference on Parallel Processing (ICPP 2007), 2007
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
IEEE Trans. Parallel Distributed Syst., 2004
IEEE Trans. Parallel Distributed Syst., 2004
IEEE Trans. Computers, 2004
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
2003
IEEE Trans. Computers, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
2002
Cache Coherence Protocol Design for Active Memory Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the 16th international conference on Supercomputing, 2002