Maik Ender

Orcid: 0000-0002-0685-2541

According to our database1, Maik Ender authored at least 16 papers between 2014 and 2024.

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Bibliography

2024
On the Malicious Potential of Xilinx's Internal Configuration Access Port (ICAP).
ACM Trans. Reconfigurable Technol. Syst., June, 2024

JustSTART: How to Find an RSA Authentication Bypass on Xilinx UltraScale(+) with Fuzzing.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Patching FPGAs: The Security Implications of Bitstream Modifications.
Proceedings of the 2024 Workshop on Attacks and Solutions in Hardware Security, 2024

2023
Targeted Bitstream Fault Fuzzing Accelerating BiFI on Large Designs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP).
Proceedings of the International Conference on Field Programmable Technology, 2023

2022
PUFs Physical Learning: Accelerating the Enrollment via Delay-Based Model Extraction.
IEEE Trans. Emerg. Top. Comput., 2022

How Not to Protect Your IP - An Industry-Wide Break of IEEE 1735 Implementations.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022

A Cautionary Note on Protecting Xilinx' UltraScale(+) Bitstream Encryption and Authentication Engine.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2020
Hardware-Trojaner.
Datenschutz und Datensicherheit, 2020

The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs.
Proceedings of the 29th USENIX Security Symposium, 2020

2019
Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Hardware Masking, Revisited.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

2017
SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA.
IACR Cryptol. ePrint Arch., 2017

The First Thorough Side-Channel Hardware Trojan.
IACR Cryptol. ePrint Arch., 2017

2014
A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014


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