Mahsa Mousavi

According to our database, Mahsa Mousavi authored at least 6 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

MTTR reduction of FPGA scrubbing: Exploring SEU sensitivity.

Mahsa Mousavi, Hamid Reza Pourshaghaghi, Akash Kumar, Henk Corporaal

Microprocess. Microsystems, 2023

2019

Fault Tolerant FPGAs: Where to Spend the Effort?

Mahsa Mousavi, Sayandip De, Hamid Reza Pourshaghaghi, Henk Corporaal

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory.

Mahsa Mousavi, Hamid Reza Pourshaghaghi, Henk Corporaal, Akash Kumar

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes.

Mahsa Mousavi, YouZhe Fan, Chi-Ying Tsui, Jie Jin, Bin Li, Hui Shen

IEEE Trans. Signal Process., 2018

Determining the necessity of fault tolerance techniques in FPGA devices for space missions.

Louis D. van Harten, Mahsa Mousavi, Roel Jordans, Hamid Reza Pourshaghaghi

Microprocess. Microsystems, 2018

A Generic Methodology to Compute Design Sensitivity to SEU in SRAM-Based FPGA.

Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Roel Jordans, Henk Corporaal

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018