Mahesh Vaidya

According to our database, Mahesh Vaidya authored at least 5 papers between 1987 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application.

Shriharsh Prasad Behera, Mahesh Vaidya, Alok Naugarhiya

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR.

Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices.

Mitesh Goyal, Mukesh Chaturvedi, Raju Kumar, Mahesh Vaidya, Mayank Shrivastava

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022

Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application.

Mahesh Vaidya, Alok Naugarhiya, Shrish Verma, Guru Prasad Mishra

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

1987

GKS implementation: A case study.

Shishir Pardikar, Mahesh Vaidya, S. S. S. P. Rao

Comput. Graph., 1987