Mahesh Vaidya

Orcid: 0000-0001-9422-415X

According to our database1, Mahesh Vaidya authored at least 5 papers between 1987 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Load-line Dependent Current Filament Dynamics in N anoscale SCR Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

2022
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

1987
GKS implementation: A case study.
Comput. Graph., 1987


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