Mahesh Kumar Adimulam

Orcid: 0000-0002-9705-1538

According to our database1, Mahesh Kumar Adimulam authored at least 16 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2022
A 12-bit, 1.1-GS/s, Low-Power Flash ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2018
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
A low power, programmable bias inverter quantizer (BIQ) flash ADC.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System.
Proceedings of the Wireless Mobile Communication and Healthcare, 2017

A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016

2011
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
Proceedings of the International Symposium on Electronic System Design, 2011

2010
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A low power, variable resolution two-step flash ADC.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.
J. Low Power Electron., 2009

Design of a Low Power, Variable-Resolution Flash ADC.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A novel low power, variable resolution pipelined ADC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009


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