Mahesh B. Patil
Orcid: 0000-0001-8766-1044
According to our database1,
Mahesh B. Patil
authored at least 30 papers
between 1998 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
Systematic equation formulation for simulation of power electronic circuits using explicit methods.
CoRR, 2024
2023
2022
2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Multi-Objective Optimisation of Damper Placement for Improved Seismic Response in Dynamically Similar Adjacent Buildings.
CoRR, 2020
2019
Water Distribution System Design Using Multi-Objective Genetic Algorithm with External Archive and Local Search.
CoRR, 2019
CoRR, 2019
2018
CoRR, 2018
2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2013
Proceedings of the IEEE Global Engineering Education Conference, 2013
2011
Microelectron. J., 2011
2010
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization.
J. Low Power Electron., 2009
Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization.
Eng. Appl. Artif. Intell., 2009
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
J. Low Power Electron., 2008
2007
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
2006
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
2003
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
2002
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
1998
VLSI Design, 1998
New discretization scheme for two-dimensional semiconductor device simulation on triangular grid.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998