Mahesh A. Iyer

According to our database, Mahesh A. Iyer authored at least 31 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Heterogeneous Acceleration System for Attention-Based Multi-Agent Reinforcement Learning.

Samuel Wiggins, Yuan Meng, Mahesh A. Iyer, Viktor K. Prasanna

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

Better Together: Combining Analytical and Annealing Methods for FPGA Placement.

Rachel Selina Rajarathnam, Kate Thurmer, Vaughn Betz, Mahesh A. Iyer, David Z. Pan

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms.

Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

A Software-Hardware Co-Optimized Toolkit for Deep Reinforcement Learning on Heterogeneous Platforms.

Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna

CoRR, 2023

DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs.

Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan

Proceedings of the 2023 International Symposium on Physical Design, 2023

2022

DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit.

Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2020

Agilex™ Generation of Intel® FPGAs.

Ilya K. Ganusov, Mahesh A. Iyer, Ning Cheng, Alon Meisler

Proceedings of the IEEE Hot Chips 32 Symposium, 2020

Symbiosis in Action: Reconfigurable Architectures and EDA.

Mahesh A. Iyer

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

High-Definition Routing Congestion Prediction for Large-Scale FPGAs.

Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

FPGA-Accelerated Spreading for Global Placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

FPGA Accelerated FPGA Placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A shape-driven spreading algorithm using linear programming for global placement.

Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2017

CAD Opportunities with Hyper-Pipelining.

Mahesh A. Iyer

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

An Effective Timing-Driven Detailed Placement Algorithm for FPGAs.

Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs.

Love Singhal, Mahesh A. Iyer, Saurabh N. Adya

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Detailed placement for modern FPGAs using 2D dynamic programming.

Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2009

On improving optimization effectiveness in interconnect-driven physical synthesis.

Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer

Proceedings of the 2009 International Symposium on Physical Design, 2009

2003

A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification.

Mahesh A. Iyer

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.

Mahesh A. Iyer

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2000

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults.

David E. Long, Mahesh A. Iyer, Miron Abramovici

ACM Trans. Design Autom. Electr. Syst., 2000

1999

High Time For High Level ATPG.

Mahesh A. Iyer

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A Robust Solution to the Timing Convergence Problem in High-Performance Design.

Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking

Proceedings of the IEEE International Conference On Computer Design, 1999

Wavefront Technology Mapping.

Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer

Proceedings of the 1999 Design, 1999

1996

FIRE: a fault-independent combinational redundancy identification algorithm.

Mahesh A. Iyer, Miron Abramovici

IEEE Trans. Very Large Scale Integr. Syst., 1996

Surprises in Sequential Redundancy Identification.

Mahesh A. Iyer, David E. Long, Miron Abramovici

Proceedings of the 1996 European Design and Test Conference, 1996

Identifying Sequential Redundancies Without Search.

Mahesh A. Iyer, David E. Long, Miron Abramovici

Proceedings of the 33st Conference on Design Automation, 1996

1995

Energy models for delay testing.

Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Identifying sequentially untestable faults using illegal states.

David E. Long, Mahesh A. Iyer, Miron Abramovici

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994

Low-Cost Redundancy Identification for Combinatorial Circuits.

Mahesh A. Iyer, Miron Abramovici

Proceedings of the Seventh International Conference on VLSI Design, 1994

Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!").

Mahesh A. Iyer, Miron Abramovici

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1992

One-Pass Redundancy Identification and Removal.

Miron Abramovici, Mahesh A. Iyer

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992