Maher Assaad
Orcid: 0000-0002-1584-8747
According to our database1,
Maher Assaad
authored at least 32 papers
between 2007 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Symmetry, July, 2024
Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.
IEEE Trans. Biomed. Circuits Syst., April, 2024
ABBD: Accumulated Band-Wise Binary Distancing for Unsupervised Parameter-Free Hyperspectral Change Detection.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2024
A Lowpass-Bandpass Triplexer With A New Microstrip Configuration and Compact Size for 5G and Energy Harvesting Applications.
IEEE Access, 2024
A Miniaturized Metamaterial-Based Dual-Band 4×4 Butler Matrix With Enhanced Frequency Ratio for Sub-6 GHz 5G Applications.
IEEE Access, 2024
Novel Ultra-Compact Wide Stopband Microstrip Lowpass-Bandpass Triplexer for 5G Multi-Service Wireless Networks.
IEEE Access, 2024
New Model For Wilson and Morris-Lecar Neuron Models: Validation and Digital Implementation on FPGA.
IEEE Access, 2024
Efficient FPGA Realization of the Memristive Wilson Neuron Model in the Face of Electromagnetic Interference.
IEEE Access, 2024
2023
A Compact Microwave Quadrature Hybrid Coupler Using Capacitive Composite Lines and Meandered Stubs.
Symmetry, December, 2023
MCCFNet: Multi-channel Color Fusion Network For Cognitive Classification of Traditional Chinese Paintings.
Cogn. Comput., November, 2023
Symmetry, August, 2023
Multivariable Signal Processing for Characterization of Failure Modes in Thin-Ply Hybrid Laminates Using Acoustic Emission Sensors.
Sensors, 2023
Design and Optimization of a Compact Microstrip Filtering Coupler With Low Losses and Improved Group Delay for High-Performance RF Communication Systems.
IEEE Access, 2023
A High-Performance Microstrip Triplexer With Compact Size, Flat Channels and Low Losses for 5G Applications.
IEEE Access, 2023
Hybrid Encoding Method for Radio Frequency Identification in the Internet of Things Systems.
IEEE Access, 2023
Hybrid Harris Hawks With Sine Cosine for Optimal Node Placement and Congestion Reduction in an Industrial Wireless Mesh Network.
IEEE Access, 2023
2022
Noninvasive Non-Contact SpO2 Monitoring Using an Integrated Polarization-Sensing CMOS Imaging Sensor.
Sensors, 2022
An Arithmetic-Trigonometric Optimization Algorithm with Application for Control of Real-Time Pressure Process Plant.
Sensors, 2022
2020
Nondestructive Food Quality Monitoring Using Phase Information in Time-Resolved Reflectance Spectroscopy.
IEEE Trans. Instrum. Meas., 2020
2019
Compressive sensing based secret signals recovery for effective image Steganalysis in secure communications.
Multim. Tools Appl., 2019
Proceedings of the UK/China Emerging Technologies, 2019
Magnetic Resonance-based Wireless Power Transfer for Implantable Biomedical Microelectronics Devices.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019
Analysis and Recovery Monitoring of Meibomian Gland Dysfunction Disease using Hyperspectral Imaging.
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
A Hardware Description Language-Based Serial Link for Multicores SoC/NoC Interconnect.
J. Low Power Electron., 2018
2017
Proceedings of the 29th International Conference on Microelectronics, 2017
2015
A 3-Bit Pseudo Flash ADC Based Low-Power CMOS Interface Circuit Design for Optical Sensor.
J. Low Power Electron., 2015
2013
Design and Characterization of Low Power and Low Noise Truly All-Digital Clock and Data Recovery Circuit for SERDES Devices.
J. Low Power Electron., 2013
2012
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture.
VLSI Design, 2012
2011
IEICE Electron. Express, 2011
An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC.
IEICE Electron. Express, 2011
2007
CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC.
Proceedings of the International Symposium on System-on-Chip, 2007