Mahendra Sakare

According to our database, Mahendra Sakare authored at least 19 papers between 2011 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning.

Sahibia Kaur Vohra, Mahendra Sakare, Alex Pappachen James, Devarshi Mrinal Das

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025

2024

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons.

Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das

Integr., March, 2024

2023

A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks.

Mayank Kumar Singh, Puneet Singh, Upendra Chichhula, Hirensh Mehra, Devarshi Mrinal Das, Mahendra Sakare

Circuits Syst. Signal Process., November, 2023

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse.

Sahibia Kaur Vohra, Sherin A. Thomas, Shivdeep, Mahendra Sakare, Devarshi Mrinal Das

IEEE Trans. Very Large Scale Integr. Syst., 2023

A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO.

Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare

Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism.

Sahibia Kaur Vohra, Alex Pappachen James, Mahendra Sakare, Devarshi Mrinal Das

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs.

Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, R. Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning.

Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das

CoRR, 2022

2021

Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing.

Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse.

Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Design of a PRBS generator and a serializer using active inductor employed CML latch.

Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A low power 8 × 2⁷-1 PRBS generator using Exclusive-OR gate merged D flip-flops.

Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2017

A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs.

Mahendra Sakare

IEEE Trans. Circuits Syst. II Express Briefs, 2017

2016

Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits.

Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture.

Mahendra Sakare

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE.

Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2014

A high-speed PRBS generator using flip-flops employing feedback for distributed equalization.

Mahendra Sakare, Shalabh Gupta

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.

Mahendra Sakare, Mohit Singh, Shalabh Gupta

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2011

Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping".

Mohit Singh, Mahendra Sakare, Shalabh Gupta

Proceedings of the Design, Automation and Test in Europe, 2011