Mahendra Rathor

Orcid: 0000-0001-8633-7322

According to our database1, Mahendra Rathor authored at least 25 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack.
IEEE Embed. Syst. Lett., June, 2024

Securing Reusable IP Cores Using Voice Biometric Based Watermark.
IEEE Trans. Dependable Secur. Comput., 2024

Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature.
IEEE Des. Test, 2024

Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng., January, 2023

Exploring Handwritten Signature Image Features for Hardware Security.
IEEE Trans. Dependable Secur. Comput., 2023

Biometrics for Hardware Security and Trust: Discussion and Analysis.
IT Prof., 2023

Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF.
IACR Cryptol. ePrint Arch., 2022

Dual-Tone Multi-Frequency Assisted Acoustic Side Channel Attack to Retrieve Dialled Call Log.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2022

Hardware (IP) Watermarking During Behavioral Synthesis.
Behavioral Synthesis for Hardware Security, 2022

2021
Facial Biometric for Securing Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Signature Biometric based Authentication of IP Cores for Secure Electronic Systems.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors.
IEEE Trans. Consumer Electron., 2020

Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems.
IEEE Trans. Consumer Electron., 2020

IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems.
IEEE Trans. Consumer Electron., 2020

Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems.
IEEE Access, 2020

Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography.
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020

2019
IP Core Steganography for Protecting DSP Kernels Used in CE Systems.
IEEE Trans. Consumer Electron., 2019

Protecting DSP Kernels Using Robust Hologram-Based Obfuscation.
IEEE Trans. Consumer Electron., 2019

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware.
IEEE Access, 2019

Robust Logic locking for Securing Reusable DSP Cores.
IEEE Access, 2019

Improved Delay Estimation Model for Loop based DSP cores.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019


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