Mahdi Nikdast
Orcid: 0000-0003-4930-2985
According to our database1,
Mahdi Nikdast
authored at least 83 papers
between 2010 and 2024.
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Bibliography
2024
ReD: A Reliable and Deadlock-Free Routing for 2.5-D Chiplet-Based Interposer Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
SwInt: A Non-Blocking Switch-Based Silicon Photonic Interposer Network for 2.5D Machine Learning Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024
Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Photonic Physically Unclonable Functions using Ring-Assisted Contra-Directional Couplers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024
SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
IEEE Des. Test, December, 2023
ACM Trans. Embed. Comput. Syst., October, 2023
AdEle+: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D Networks-on-Chip.
IEEE Trans. Computers, August, 2023
IEEE Des. Test, April, 2023
CoRR, 2023
Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks.
CoRR, 2023
IEEE Access, 2023
RISA: Round-Robin Intra-Rack Friendly Scheduling Algorithm for Disaggregated Datacenters.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the 34th International Workshop on Rapid System Prototyping, 2023
Proceedings of the International Conference on Photonics in Switching and Computing, 2023
Integrated Photonic AI Accelerators Under Hardware Security Attacks: Impacts and Countermeasures.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
TRINE: A Tree-Based Silicon Photonic Interposer Network for Energy-Efficient 2.5D Machine Learning Acceleration.
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study.
ACM J. Emerg. Technol. Comput. Syst., 2022
CoRR, 2022
Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations.
CoRR, 2022
CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
A Silicon Photonic Accelerator for Convolutional Neural Networks with Heterogeneous Quantization.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
SONIC: A Sparse Neural Network Inference Accelerator with Silicon Photonics for Energy-Efficient Deep Learning.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
ACM Trans. Embed. Comput. Syst., 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Des. Test, 2020
LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
2018
DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
IEEE Embed. Syst. Lett., 2017
2016
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks.
IEEE Commun. Lett., 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Computers, 2014
ACM J. Emerg. Technol. Comput. Syst., 2014
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2014
IEEE Des. Test, 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst., 2012
2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2010
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the 47th Design Automation Conference, 2010