Mahdi Nazemi
Orcid: 0000-0003-4731-3568
According to our database1,
Mahdi Nazemi
authored at least 27 papers
between 2015 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
Memory-Efficient Vision Transformers: An Activation-Aware Mixed-Rank Compression Strategy.
CoRR, 2024
NeuroBlend: Towards Low-Power yet Accurate Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis.
ACM Trans. Reconfigurable Technol. Syst., June, 2023
Sensitivity-Aware Mixed-Precision Quantization and Width Optimization of Deep Neural Networks Through Cluster-Based Tree-Structured Parzen Estimation.
CoRR, 2023
BlendNet: Design and Optimization of a Neural Network-Based Inference Engine Blending Binary and Fixed-Point Convolutions.
CoRR, 2023
SNT: Sharpness-Minimizing Network Transformation for Fast Compression-friendly Pretraining.
CoRR, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Computers, 2020
CoRR, 2020
SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
Energy-efficient, low-latency realization of neural networks through boolean logic minimization.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
CoRR, 2018
A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015