Mahdi Fazeli
Orcid: 0000-0002-2874-6256
According to our database1,
Mahdi Fazeli
authored at least 87 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
Optimized reverse converters with multibit soft error correction support at 7nm technology.
Comput. Electr. Eng., April, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Detection of Application-Layer DDoS Attacks Produced by Various Freely Accessible Toolkits Using Machine Learning.
IEEE Access, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
2022
A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints.
Microprocess. Microsystems, November, 2022
Microprocess. Microsystems, March, 2022
J. Supercomput., 2022
MagCiM: A Flexible and Non-Volatile Computing-in-Memory Processor for Energy-Efficient Logic Computation.
IEEE Access, 2022
Application Layer DDoS Attack Detection Using Cuckoo Search Algorithm-Trained Radial Basis Function.
IEEE Access, 2022
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022
2021
ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology.
IEEE Trans. Computers, 2021
NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications.
IEEE Trans. Computers, 2021
Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits.
J. Circuits Syst. Comput., 2021
Integr., 2021
CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes.
Cryptogr., 2021
Efficient Scheduling of Dependent Tasks in Many-Core Real-Time System Using a Hardware Scheduler.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
ACM Trans. Embed. Comput. Syst., 2020
IET Inf. Secur., 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
2019
RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Ultra-low power and reliable magnetic based interconnects for nano-scale technologies.
Microelectron. J., 2019
An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors.
J. Circuits Syst. Comput., 2019
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
2018
Int. J. Parallel Program., 2018
IET Inf. Secur., 2018
J. Electron. Test., 2018
Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
2017
ISC Int. J. Inf. Secur., 2017
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.
IET Comput. Digit. Tech., 2017
Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
Turkish J. Electr. Eng. Comput. Sci., 2017
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
Proceedings of the Knowledge Science, Engineering and Management, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Reliability-oriented scheduling for static-priority real-time tasks in standby-sparing systems.
Microprocess. Microsystems, 2016
Unauthenticated event detection in wireless sensor networks using sensors co-coverage.
ISC Int. J. Inf. Secur., 2016
IET Comput. Digit. Tech., 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
2015
An Efficient Data Aggregation Method for Event-Driven WSNs: A Modeling and Evaluation Approach.
Wirel. Pers. Commun., 2015
Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations.
J. Circuits Syst. Comput., 2015
2014
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates.
Microelectron. Reliab., 2014
Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients.
J. Circuits Syst. Comput., 2014
IEEE Comput. Archit. Lett., 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation.
Microelectron. Reliab., 2013
Math. Comput. Model., 2013
Bee-MMT: A load balancing method for power consumption management in cloud computing.
Proceedings of the Sixth International Conference on Contemporary Computing, 2013
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013
Proceedings of the 2013 Eighth International Conference on Broadband and Wireless Computing, 2013
2012
Microelectron. Reliab., 2012
Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors.
Proceedings of the 2012 Ninth European Dependable Computing Conference, 2012
2011
Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors.
Microelectron. Reliab., 2011
Software-based control flow error detection and correction using branch triplication.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011
Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).
Proceedings of the Design, Automation and Test in Europe, 2011
2010
A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies.
IET Comput. Digit. Tech., 2009
An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009
2008
J. Electron. Test., 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 11th IEEE High Assurance Systems Engineering Symposium, 2008
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption.
Proceedings of the The Third International Conference on Availability, 2008
2007
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007
Reducing Power Consumption in NoC Design with no Effect on Performance and Reliability.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007
Distance-Based Segmentation: An Energy-Efficient Clustering Hierarchy for Wireless Microsensor Networks.
Proceedings of the Fifth Annual Conference on Communication Networks and Services Research (CNSR 2007), 2007
2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
A Solution to Single Point of Failure Using Voter Replication and Disagreement Detection.
Proceedings of the Second International Symposium on Dependable Autonomic and Secure Computing (DASC 2006), 29 September, 2006
2005
A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the Systems Communications 2005 (ICW / ICHSN / ICMCS / SENET 2005), 2005
Proceedings of the Distributed and Parallel Computing, 2005
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005