Mahdi Fazeli

Orcid: 0000-0002-2874-6256

According to our database1, Mahdi Fazeli authored at least 87 papers between 2005 and 2024.

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Bibliography

2024
Advancing IoT Security Through Run-time Monitoring & Post-Execution Verification.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023
Optimized reverse converters with multibit soft error correction support at 7nm technology.
Comput. Electr. Eng., April, 2023

WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges.
IEEE Trans. Emerg. Top. Comput., 2023

Detection of Application-Layer DDoS Attacks Produced by Various Freely Accessible Toolkits Using Machine Learning.
IEEE Access, 2023

Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

2022
A security-aware hardware scheduler for modern multi-core systems with hard real-time constraints.
Microprocess. Microsystems, November, 2022

CyEnSe: Cyclic energy-aware scheduling for energy-harvested embedded systems.
Microprocess. Microsystems, March, 2022

A multi-application approach for synthesizing custom network-on-chips.
J. Supercomput., 2022

MagCiM: A Flexible and Non-Volatile Computing-in-Memory Processor for Energy-Efficient Logic Computation.
IEEE Access, 2022

Application Layer DDoS Attack Detection Using Cuckoo Search Algorithm-Trained Radial Basis Function.
IEEE Access, 2022

An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

A Low-Cost Stochastic Computing-based Fuzzy Filtering for Image Noise Reduction.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

2021
ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology.
IEEE Trans. Computers, 2021

NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications.
IEEE Trans. Computers, 2021

Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits.
J. Circuits Syst. Comput., 2021

An energy efficient synthesis flow for application specific SoC design.
Integr., 2021

CONFISCA: An SIMD-Based Concurrent FI and SCA Countermeasure with Switchable Performance and Security Modes.
Cryptogr., 2021

Efficient Scheduling of Dependent Tasks in Many-Core Real-Time System Using a Hardware Scheduler.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
Design Space Exploration for Ultra-Low-Energy and Secure IoT MCUs.
ACM Trans. Embed. Comput. Syst., 2020

Scan-based attack tolerance with minimum testability loss: a gate-level approach.
IET Inf. Secur., 2020

Enduring Non-Volatile L1 Cache Using Low-Retention-Time STTRAM Cells.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Fuzzy-Logic using Unary Bit-Stream Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019
RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Ultra-low power and reliable magnetic based interconnects for nano-scale technologies.
Microelectron. J., 2019

An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors.
J. Circuits Syst. Comput., 2019

Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

2018
An Efficient Programming Skeleton for Clusters of Multi-Core Processors.
Int. J. Parallel Program., 2018

Vulnerability modelling of crypto-chips against scan-based attacks.
IET Inf. Secur., 2018

Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing.
J. Electron. Test., 2018

Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017
Side channel parameter characteristics of code injection attacks.
ISC Int. J. Inf. Secur., 2017

Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file.
IET Comput. Digit. Tech., 2017

Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology.
Turkish J. Electr. Eng. Comput. Sci., 2017

Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

ARMICA-Improved: A New Approach for Association Rule Mining.
Proceedings of the Knowledge Science, Engineering and Management, 2017

2016
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability-oriented scheduling for static-priority real-time tasks in standby-sparing systems.
Microprocess. Microsystems, 2016

Unauthenticated event detection in wireless sensor networks using sensors co-coverage.
ISC Int. J. Inf. Secur., 2016

Phase Change Memory lifetime enhancement via online data swapping.
Integr., 2016

Performance/energy aware task migration algorithm for many-core chips.
IET Comput. Digit. Tech., 2016

Hardware enlightening: No where to hide your Hardware Trojans!
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

High output hamming-distance achievement by a greedy logic masking approach.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015
An Efficient Data Aggregation Method for Event-Driven WSNs: A Modeling and Evaluation Approach.
Wirel. Pers. Commun., 2015

Single Event Multiple Upset (SEMU) Tolerant Latch Designs in Presence of Process and Temperature Variations.
J. Circuits Syst. Comput., 2015

2014
Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates.
Microelectron. Reliab., 2014

Soft error rate estimation for Combinational Logic in Presence of Single Event Multiple Transients.
J. Circuits Syst. Comput., 2014

Coding Last Level STT-RAM Cache for High Endurance and Low Power.
IEEE Comput. Archit. Lett., 2014

2013
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation.
Microelectron. Reliab., 2013

A parallel clustering algorithm on the star graph and its performance.
Math. Comput. Model., 2013

Bee-MMT: A load balancing method for power consumption management in cloud computing.
Proceedings of the Sixth International Conference on Contemporary Computing, 2013

FTSPM: A Fault-Tolerant ScratchPad Memory.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

OLDA: An Efficient On-Line Data Aggregation Method for Wireless Sensor Networks.
Proceedings of the 2013 Eighth International Conference on Broadband and Wireless Computing, 2013

2012
Efficient algorithms to accurately compute derating factors of digital circuits.
Microelectron. Reliab., 2012

Memory Mapped SPM: Protecting Instruction Scratchpad Memory in Embedded Systems against Soft Errors.
Proceedings of the 2012 Ninth European Dependable Computing Conference, 2012

2011
Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors.
Microelectron. Reliab., 2011

Software-based control flow error detection and correction using branch triplication.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A Low Cost circuit level fault detection technique to Full Adder design.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Low Cost Concurrent Error Detection for On-Chip Memory Based Embedded Processors.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs).
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A low-overhead and reliable switch architecture for Network-on-Chips.
Integr., 2010

A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design.
Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, 2010

A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies.
IET Comput. Digit. Tech., 2009

An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2008
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors.
J. Electron. Test., 2008

A Power Efficient Approach to Fault-Tolerant Register File Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Low Energy Soft Error-Tolerant Register File Architecture for Embedded Processors.
Proceedings of the 11th IEEE High Assurance Systems Engineering Symposium, 2008

A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

FEDC: Control Flow Error Detection and Correction for Embedded Systems without Program Interruption.
Proceedings of the The Third International Conference on Availability, 2008

2007
A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007

Reducing Power Consumption in NoC Design with no Effect on Performance and Reliability.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

Distance-Based Segmentation: An Energy-Efficient Clustering Hierarchy for Wireless Microsensor Networks.
Proceedings of the Fifth Annual Conference on Communication Networks and Services Research (CNSR 2007), 2007

2006
Transient Error Detection in Embedded Systems Using Reconfigurable Components.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

A Software-Based Error Detection Technique Using Encoded Signatures.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A Solution to Single Point of Failure Using Voter Replication and Disagreement Detection.
Proceedings of the Second International Symposium on Dependable Autonomic and Secure Computing (DASC 2006), 29 September, 2006

2005
A Fault Tolerant Approach to Object Oriented Design and Synthesis of Embedded Systems.
Proceedings of the Dependable Computing, Second Latin-American Symposium, 2005

A Cordic-Based Processor Extension for Scalar and Vector Processing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Directed Flooding: A Fault-Tolerant Routing Protocol for Wireless Sensor Networks.
Proceedings of the Systems Communications 2005 (ICW / ICHSN / ICMCS / SENET 2005), 2005

Parallel Clustering on the Star Graph.
Proceedings of the Distributed and Parallel Computing, 2005

A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005


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