Maha Kooli

According to our database, Maha Kooli authored at least 25 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip.

Xabier Iturbe, Bernabé Linares-Barranco, Sio-Hoi Ieng, Arne Erdmann, Luca Peres, Oliver Rhodes, Rafael Tornero, Manolis Sifalakis, Marcel D. van de Burgwal, Amirreza Yousefzadeh, Maha Kooli, Riccardo Alidori, Pavel Zaykov

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units.

Kevin Mambu, Henri-Pierre Charles, Maha Kooli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.

Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator.

Kevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli

Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Data-layout optimization based on memory-access-pattern analysis for source-code performance improvement.

Riyane Sid Lakhdar, Henri-Pierre Charles, Maha Kooli

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.

Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.

Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.

Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo

IEEE Trans. Computers, 2019

Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems.

Maha Kooli, Giorgio Di Natale, Alberto Bosio

J. Electron. Test., 2019

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture.

Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization.

Riyane Sid Lakhdar, Henri-Pierre Charles, Maha Kooli

Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

2018

Smart instruction codes for in-memory computing architectures compatible with standard SRAM interfaces.

Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Computing reliability: On the differences between software testing and software fault injection techniques.

Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres

Microprocess. Microsystems, 2017

Software platform dedicated for in-memory computing circuit evaluation.

Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noël

Proceedings of the International Symposium on Rapid System Prototyping, 2017

Reliability of computing systems: From flip flops to variables.

Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

Cache- and register-aware system reliability evaluation based on data lifetime analysis.

Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cross-layer system reliability assessment framework for hardware faults.

Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale

Proceedings of the 2016 IEEE International Test Conference, 2016

Cache-aware reliability evaluation through LLVM-based analysis and fault injection.

Maha Kooli, Giorgio Di Natale, Alberto Bosio

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

System-level reliability evaluation through cache-aware software-based fault injection.

Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.

Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo

Microprocess. Microsystems, 2015

Software testing and software fault injection.

Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Fault injection tools based on Virtual Machines.

Maha Kooli, Pascal Benoit, Giorgio Di Natale, Lionel Torres, Volkmar Sieh

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

A survey on simulation-based fault injection tools for complex systems.

Maha Kooli, Giorgio Di Natale

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014