Magnus Jahre
Orcid: 0000-0001-9147-5228
According to our database1,
Magnus Jahre
authored at least 61 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Micro, 2024
Proceedings of the 2nd Workshop on SErverless Systems, Applications and MEthodologies, 2024
AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
ACM Trans. Archit. Code Optim., December, 2023
Future Gener. Comput. Syst., 2023
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
ESS: Repeatable Evaluation of Energy Harvesting Subsystems for Industry-Grade IoT Platforms.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
IEEE Comput. Archit. Lett., 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
2021
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode.
J. Signal Process. Syst., 2021
IEEE Comput. Archit. Lett., 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020
2019
CoRR, 2019
IEEE Comput. Archit. Lett., 2019
2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Proceedings of the Scaling OpenMP for Exascale Performance and Portability, 2017
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017
DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Towards efficient quantized neural network inference on mobile devices: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017
2016
Microprocess. Microsystems, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
ACM Trans. Archit. Code Optim., 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the Architecture of Computing Systems - ARCS 2014, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Proceedings of the International Conference on Computational Science, 2013
2011
Trans. High Perform. Embed. Archit. Compil., 2011
J. Instr. Level Parallelism, 2011
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011
2010
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010
2009
Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals.
IEEE Trans. Educ., 2009
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009
Proceedings of the 6th Conference on Computing Frontiers, 2009
2008
Proceedings of the 26th International Conference on Computer Design, 2008