Magdy S. Abadir

According to our database, Magdy S. Abadir authored at least 147 papers between 1983 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber

IEEE Trans. Very Large Scale Integr. Syst., 2019

2017

Challenges and Trends in Modern SoC Design Verification.

Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang

IEEE Des. Test, 2017

Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification.

Magdy S. Abadir, Jayanta Bhadra, Wen Chen, Li-C. Wang

IEEE Des. Test, 2017

2014

Yield optimization using advanced statistical correlation methods.

Jeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2014 International Test Conference, 2014

Multivariate outlier modeling for capturing customer returns - How simple it can be.

Jeff Tikkanen, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Data Mining In EDA - Basic Principles, Promises, and Constraints.

Li-C. Wang, Magdy S. Abadir

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.

Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C. Wang

J. Electron. Test., 2013

Keynote 1 - VLSI 2.0: R&D Post Moore.

Sani R. Nassif, Yale N. Patt, Magdy S. Abadir

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Novel test analysis to improve structural coverage - A commercial experiment.

Wen Chen, Li-C. Wang, Jayanta Bhadra, Magdy S. Abadir

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A pattern mining framework for inter-wafer abnormality analysis.

Nik Sumikawa, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2013 IEEE International Test Conference, 2013

Simulation knowledge extraction and reuse in constrained random processor verification.

Wen Chen, Li-C. Wang, Jay Bhadra, Magdy S. Abadir

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Introduction to special section on verification challenges in the concurrent world.

Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta

ACM Trans. Design Autom. Electr. Syst., 2012

Data mining based prediction paradigm and its applications in design automation.

Magdy S. Abadir, Nik Sumikawa, Wen Chen, Li-C. Wang

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An experiment of burn-in time reduction based on parametric test analysis.

Nik Sumikawa, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2012 IEEE International Test Conference, 2012

Screening customer returns with multivariate test analysis.

Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir

Proceedings of the 2012 IEEE International Test Conference, 2012

Novel test detection to improve simulation efficiency - A commercial experiment.

Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, Magdy S. Abadir

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Understanding customer returns from a test perspective.

Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Forward prediction based on wafer sort data - A case study.

Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir

Proceedings of the 2011 IEEE International Test Conference, 2011

Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits.

Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch.

Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir

IEEE Des. Test Comput., 2010

Design for reality: knowledge discovery in design and test data.

Magdy S. Abadir

Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Coverage metrics for verification of concurrent SystemC designs using mutation testing.

Alper Sen, Magdy S. Abadir

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch.

Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir

Proceedings of the 47th Design Automation Conference, 2010

2009

A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch.

Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Minimizing outlier delay test cost in the presence of systematic variability.

Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2009 IEEE International Test Conference, 2009

TRAM: A tool for Temperature and Reliability Aware Memory Design.

Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Validating Power Architecture^TM Technology-Based MPSoCs Through Executable Specifications.

Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir

IEEE Trans. Very Large Scale Integr. Syst., 2008

Linking Statistical Learning to Diagnosis.

Pouria Bastani, Li-C. Wang, Magdy S. Abadir

IEEE Des. Test Comput., 2008

Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained.

Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2008 IEEE International Test Conference, 2008

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Predictive runtime verification of multi-processor SoCs in SystemC.

Alper Sen, Vinit Ogale, Magdy S. Abadir

Proceedings of the 45th Design Automation Conference, 2008

Statistical diagnosis of unmodeled systematic timing effects.

Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir

Proceedings of the 45th Design Automation Conference, 2008

2007

A Survey of Hybrid Techniques for Functional Verification.

Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray

IEEE Des. Test Comput., 2007

Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.

Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang

IEEE Des. Test Comput., 2007

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Statistical analysis and optimization of parametric delay test.

Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2007 IEEE International Test Conference, 2007

Analyzing the risk of timing modeling based on path delay tests.

Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir

Proceedings of the 2007 IEEE International Test Conference, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.

Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Design-Silicon Timing Correlation A Data Mining Perspective.

Li-C. Wang, Pouria Bastani, Magdy S. Abadir

Proceedings of the 44th Design Automation Conference, 2007

LEAF: A System Level Leakage-Aware Floorplanner for SoCs.

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A Trace-Driven Validation Methodology for Multi-Processor SOCS.

Jayanta Bhadra, Ekaterina Trofimova, Leonard J. Giordano, Magdy S. Abadir

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.

Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir

Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective.

Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir

Proceedings of the 2006 IEEE International Test Conference, 2006

Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs.

Magdy S. Abadir

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Extracting a Simplified View of Design Functionality Based on Vector Simulation.

Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir

Proceedings of the Hardware and Software, 2006

Extracting a simplified view of design functionality via vector simulation.

Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Refined statistical static timing analysis through.

Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir

Proceedings of the 43rd Design Automation Conference, 2006

Floorplan driven leakage power aware IP-based SoC design space exploration.

Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

A methodology for validation of microprocessors using symbolic simulation.

Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir

Int. J. Embed. Syst., 2005

Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG.

Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi

J. Electron. Test., 2005

Reducing Pattern Delay Variations for Screening Frequency Dependent Defects.

Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Recent Advances in Verification, Equivalence Checking and SAT-Solvers.

Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Retiming Verification Using Sequential Equivalence Checking.

Brian Kahne, Magdy S. Abadir

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.

Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects.

Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Post-verification debugging of hierarchical designs.

Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Establishing latch correspondence for embedded circuits of PowerPC microprocessors.

Himyanshu Anand, Jayanta Bhadra, Alper Sen, Magdy S. Abadir, Kenneth G. Davis

Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Diagnosing multiple transition faults in the absence of timing information.

Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Choosing flows and methodologies for SoC design.

Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris

Proceedings of the 42nd Design Automation Conference, 2005

2004

IDAP: a tool for high-level power estimation of custom array structures.

Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Top-Down Methodology for Microprocessor Validation.

Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir

IEEE Des. Test Comput., 2004

Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir

IEEE Des. Test Comput., 2004

Guest Editors' Introduction: The Verification and Test of Complex Digital ICs.

Magdy S. Abadir, Li-C. Wang

IEEE Des. Test Comput., 2004

Towards The Complete Elimination of Gate/Switch Level Simulations.

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.

Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Identification of Gates for Covering all Critical Paths.

M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.

Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Fault equivalence and diagnostic test generation using ATPG.

Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Debugging sequential circuits using Boolean satisfiability.

Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

On path-based learning and its applications in delay test and diagnosis.

Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir

Proceedings of the 41th Design Automation Conference, 2004

Analytical models for leakage power estimation of memory array structures.

Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Formal Verification Successes at Motorola.

Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin

Formal Methods Syst. Des., 2003

Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems.

Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey

Des. Autom. Embed. Syst., 2003

Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs.

Magdy S. Abadir, Juhong Zhu

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.

Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir

Proceedings of the 2003 Design, 2003

Automated Test Model Generation from Switch Level Custom Circuits.

Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Logic verification based on diagnosis techniques.

Andreas G. Veneris, Alexander Smith, Magdy S. Abadir

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

An automated method for test model generation from switch level circuits.

Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Enhanced symbolic simulation for efficient verification of embedded array systems.

Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design rewiring using ATPG.

Andreas G. Veneris, Magdy S. Abadir

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Validation and Verification of Complex Digital Systems: A Practical Perspective.

Li-C. Wang, Magdy S. Abadir

Proceedings of the 3rd Latin American Test Workshop, 2002

Efficient and Exact Diagnosis of Multiple Stuck-At Faults.

Jiang Brandon Liu, Andreas G. Veneris, Magdy S. Abadir

Proceedings of the 3rd Latin American Test Workshop, 2002

On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.

Li-C. Wang, Magdy S. Abadir, Juhong Zhu

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Design Rewiring Using ATPG.

Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.

Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Incremental Diagnosis and Correction of Multiple Faults and Errors.

Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir

Proceedings of the 2002 Design, 2002

Minimal Test for Coupling Faults in Word-Oriented Memories.

Ad J. van de Goor, Magdy S. Abadir, Alan Carlin

Proceedings of the 2002 Design, 2002

False timing path identification using ATPG techniques and delay-based information.

Jing Zeng, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 39th Design Automation Conference, 2002

2001

Design and Development Paradigm for Industrial Formal Verification CAD Tools.

Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham

IEEE Des. Test Comput., 2001

Very Low Cost Testers: Opportunities and Challenges.

Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir

IEEE Des. Test Comput., 2001

Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.

Magdy S. Abadir, Juhong Zhu, Li-C. Wang

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

ATPG for Design Errors-Is It Possible?

Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

ATPG Driven Logic Synthesis for Delay and Power Minimization.

Ivor Ting, Andreas G. Veneris, Magdy S. Abadir

Proceedings of the 2nd Latin American Test Workshop, 2001

Verification and Validation of Complex Digital Systems: An Industrial Perspective.

Magdy S. Abadir, Li-C. Wang

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.

Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A language formalism for verification of PowerPC^TM custom memories using compositions of abstract specifications.

Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Full chip false timing path identification: applications to the PowerPCTM microprocessors.

Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using Abstract Specifications to Verify PowerPC^TM Custom Memories by Symbolic Trajectory Evaluation.

Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir

Proceedings of the Correct Hardware Design and Verification Methods, 2001

Design rewiring based on diagnosis techniques.

Andreas G. Veneris, Magdy S. Abadir, Ivor Ting

Proceedings of ASP-DAC 2001, 2001

2000

Oscillation Ring Delay Test for High Performance Microprocessors.

Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir

J. Electron. Test., 2000

On Efficiently Producing Quality Tests for Custom Circuits in PowerPC^TM Microprocessors.

Li-C. Wang, Magdy S. Abadir

J. Electron. Test., 2000

Guest Editorial.

Magdy S. Abadir

J. Electron. Test., 2000

Validating PowerPC Microprocessor Custom Memories.

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham

IEEE Des. Test Comput., 2000

Guest Editors' Introduction: Microprocessor Test and Verification.

Magdy S. Abadir, Sumit Dasgupta

IEEE Des. Test Comput., 2000

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Design Optimization Based on Diagnosis Techniques.

Andreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji

Proceedings of the 1st Latin American Test Workshop, 2000

A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC Microprocessor.

Jayanta Batra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 1st Latin American Test Workshop, 2000

A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC^TM microprocessor.

Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.

Li-C. Wang, Magdy S. Abadir

J. Electron. Test., 1999

Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.

Li-C. Wang, Magdy S. Abadir

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Design-for-test methodology for Motorola PowerPC microprocessors.

Magdy S. Abadir, Rajesh Raina

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.

Li-C. Wang, Magdy S. Abadir, Jing Zeng

ACM Trans. Design Autom. Electr. Syst., 1998

Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.

Li-C. Wang, Magdy S. Abadir

J. Electron. Test., 1998

On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.

Li-C. Wang, Magdy S. Abadir, Jing Zeng

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.

Arun Chandra, Li-C. Wang, Magdy S. Abadir

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.

Li-C. Wang, Magdy S. Abadir, Jing Zeng

Proceedings of the 1998 Design, 1998

Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.

Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy

Proceedings of the 35th Conference on Design Automation, 1998

1997

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.

Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell

IEEE Trans. Computers, 1997

Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.

Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn

J. Electron. Test., 1997

Design and Test Economics-An Extra Dimension.

Tony Ambler, Magdy S. Abadir

IEEE Des. Test Comput., 1997

Cost-Driven Ranking of Memory Elements for Partial Intrusion.

Magdy S. Abadir, Rohit Kapur

IEEE Des. Test Comput., 1997

Microprocessor Test and Validation: Any New Avenues?

Magdy S. Abadir, Jacob A. Abraham, Hong Hao, C. Hunter, Wayne M. Needham, Ron G. Walther

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A New Validation Methodology Combining Test and Formal Verification for PowerPC^TM Microprocessor Arrays.

Li-C. Wang, Magdy S. Abadir

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.

Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir

Proceedings of the 34st Conference on Design Automation, 1997

1996

PowerPC^TM Array Verification Methodology using Formal Techniques.

Neeta Ganguly, Magdy S. Abadir, Manish Pandey

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1994

Multichip systems trade-off analysis tool.

Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh

J. Electron. Test., 1994

High Level Test Economics Advisor (Hi-TEA).

Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy

J. Electron. Test., 1994

Introduction.

Magdy S. Abadir, Tony Ambler

J. Electron. Test., 1994

Analyzing Multichip Module Testing Strategies.

Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake

IEEE Des. Test Comput., 1994

Efficient Algorithmic Circuit Verification Using Indexed BDDs.

James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell

Proceedings of the Digest of Papers: FTCS/24, 1994

1993

AMBIANT: Automatic Generation of Behavioral Modifications for Testability.

Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

Automatic Test Knowledge Extraction from VHDL (ATKET).

Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir

Proceedings of the 29th Design Automation Conference, 1992

1991

Partitioning Hierarchical Designs for Testability.

Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

An improved layout verification algorithm (LAVA).

Magdy S. Abadir, Jack Ferguson

Proceedings of the European Design Automation Conference, 1990

1989

TIGER: testability insertion guidance expert system.

Magdy S. Abadir

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Logic design verification via test generation.

Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

1986

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams.

Magdy S. Abadir, Hassan K. Reghbati

IEEE Trans. Computers, 1986

Test Schedules for VLSI Circuits Having Built-In Test Hardware.

Magdy S. Abadir, Melvin A. Breuer

IEEE Trans. Computers, 1986

Scan Path with Look Ahead Shifting (SPLASH).

Magdy S. Abadir, Melvin A. Breuer

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

A Knowledge-Based System for Designing Testable VLSI Chips.

Magdy S. Abadir, Melvin A. Breuer

IEEE Des. Test, 1985

Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams.

Magdy S. Abadir, Hassan K. Reghbati

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Test generation for LSI: A case study.

Magdy S. Abadir, Hassan K. Reghbati

Proceedings of the 21st Design Automation Conference, 1984

1983

LSI Testing Techniques.

Magdy S. Abadir, Hassan K. Reghbati

IEEE Micro, 1983

Functional Testing of Semiconductor Random Access Memories.

Magdy S. Abadir, Hassan K. Reghbati

ACM Comput. Surv., 1983