Madhura Purnaprajna
Orcid: 0000-0003-4995-6233
According to our database1,
Madhura Purnaprajna
authored at least 27 papers
between 2004 and 2023.
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Bibliography
2023
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders.
IEEE Des. Test, February, 2023
2022
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures.
IEEE Commun. Surv. Tutorials, 2022
MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2021
Microprocess. Microsystems, 2021
Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
2020
Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
2018
TileNET: Scalable Architecture for High-Throughput Ternary Convolution Neural Networks Using FPGAs.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Streaming Tiles: Flexible Implementation of Convolution Neural Networks Inference on Manycore Architectures.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018
Performance modeling for data distribution in heterogeneous computing systems: work in progress.
Proceedings of the International Conference on Compilers, 2018
2015
ACM Trans. Embed. Comput. Syst., 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
2010
ACM Trans. Reconfigurable Technol. Syst., 2010
2009
SIGARCH Comput. Archit. News, 2009
Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Genetic algorithms for hardware-software partitioning and optimal resource allocation.
J. Syst. Archit., 2007
2004
Genetic Algorithms in Hardware-Software Partitioning.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004