Madhu K. Iyer

According to our database, Madhu K. Iyer authored at least 13 papers between 1999 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

RTL SAT simplification by Boolean and interval arithmetic reasoning.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An Efficient Sequential SAT Solver With Improved Search Strategies.

Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen

Proceedings of the 2005 Design, 2005

Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver.

Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng

Proceedings of the 2005 Design, 2005

Structural search for RTL with predicate learning.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer

Proceedings of the 42nd Design Automation Conference, 2005

2004

Safety Property Verification Using Sequential SAT and Bounded Model Checking.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

IEEE Des. Test Comput., 2004

An efficient finite-domain constraint solver for circuits.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 41th Design Automation Conference, 2004

Efficient reachability checking using sequential SAT.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

SATORI - A Fast Sequential SAT Engine for Circuits.

Madhu K. Iyer, Ganapathy Parthasarathy, Kwang-Ting Cheng

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A comparison of BDDs, BMC, and sequential SAT for model checking.

Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

2002

Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs.

Madhu K. Iyer, Kwang-Ting Cheng

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.

Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.

Jing-Reng Huang, Madhu K. Iyer, Kwang-Ting Cheng

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

1999

Effect of Noise on Analog Circuit Testing.

Madhu K. Iyer, Michael L. Bushnell

J. Electron. Test., 1999