Madheswaran Muthusamy

Orcid: 0000-0003-0152-8037

According to our database1, Madheswaran Muthusamy authored at least 4 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Design of an Area Efficient and High-Performance Adder with a Novel Sum Generator.
Circuits Syst. Signal Process., September, 2024

2021
Wavelet neural learning-based type-2 fuzzy PID controller for speed regulation in BLDC motor.
Neural Comput. Appl., 2021

An intelligent hybrid interfacing converter of fuel cell powered telecom loads for efficient power conversion.
Comput. Electr. Eng., 2021

2019
FPGA implementation of IFFT architecture with enhanced pruning algorithm for low power application.
Microprocess. Microsystems, 2019


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