Madhav Pathak

Orcid: 0000-0002-3056-3918

According to our database1, Madhav Pathak authored at least 6 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Dynamic Resistance Reduction Methods for Voltage Clamp Lowering to Enhance GGNMOS ESD Protection.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2023
A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
High-Voltage Triboelectric Energy Harvesting Using Multi-Shot Energy Extraction in 70-V BCD Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
Synchronous Pre-biasing of Triboelectric Nanogenerator for Enhanced Energy Extraction.
CoRR, 2021

Synchronous Inductor Switched Energy Extraction Circuits for Triboelectric Nanogenerator.
IEEE Access, 2021

2019
Pre-Biased Synchronous Charge Extraction for Triboelectric Nanogenerator.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019


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