Madhav P. Desai
Affiliations:- Indian Institute of Technology Bombay, Mumbai, India
- University of Illinois at Urbana-Champaign, Urbana, IL, USA (PhD)
According to our database1,
Madhav P. Desai
authored at least 48 papers
between 1993 and 2025.
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Bibliography
2025
Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device.
Int. J. Inf. Sec., February, 2025
2024
Proceedings of the Winter Simulation Conference, 2024
2023
An evaluation of a microprocessor with two independent hardware execution threads coupled through a shared cache.
CoRR, 2023
2022
Sitar: A Cycle-based Discrete-Event Simulation Framework for Architecture Exploration.
Proceedings of the 12th International Conference on Simulation and Modeling Methodologies, 2022
2021
An efficient reverse-lookup table based strategy for solving the synonym and cache coherence problem in virtually indexed, virtually tagged caches.
CoRR, 2021
2018
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology.
Microelectron. J., 2018
2017
CoRR, 2017
2016
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates.
CoRR, 2016
Projective cofactor decompositions of Boolean functions and the satisfiability problem.
CoRR, 2016
Low-Power, Low-Latency Hermite Polynomial Characterization of Heartbeats Using a Field-Programmable Gate Array.
Proceedings of the Bioinformatics and Biomedical Engineering, 2016
2015
An Approach to Discrete Parameter Design Space Exploration of Multi-core Systems Using a Novel Simulation Based Interpolation Technique.
Proceedings of the 23rd IEEE International Symposium on Modeling, 2015
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
Optimization of Discrete-parameter Multiprocessor Systems using a Novel Ergodic Interpolation Technique.
CoRR, 2014
CoRR, 2014
2012
Proceedings of the 2012 USENIX Annual Technical Conference, 2012
2010
Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009
2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
2005
Proceedings of the 3rd International Symposium on Modeling and Optimization in Mobile, 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
IEEE J. Sel. Areas Commun., 2003
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function.
Discret. Appl. Math., 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
2002
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
Microelectron. Reliab., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1998
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor.
Proceedings of the 35th Conference on Design Automation, 1998
1996
A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation.
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 33st Conference on Design Automation, 1996
1994
1993
SIAM J. Matrix Anal. Appl., October, 1993