Maciej J. Ciesielski

According to our database, Maciej J. Ciesielski authored at least 110 papers between 1981 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2024

Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers.

Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski

Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024

Combining Formal Verification and Testing for Debugging of Arithmetic Circuits.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Formal Verification of Divider Circuits by Hardware Reduction.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 19th International Conference on Synthesis, 2023

Efficient Formal Verification and Debugging of Arithmetic Divider Circuits.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Formal Methods in Arithmetic Circuit Verification: A Brief History and Look into the Future.

Maciej J. Ciesielski

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Formal Verification of Restoring Dividers made Fast and Simple.

Jiteshri Dasari, Maciej J. Ciesielski

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Functional Verification of Arithmetic Circuits: Survey of Formal Methods.

Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2020

Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model.

Maciej J. Ciesielski, Tiankai Su, Atif Yasin, Cunxi Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach.

Tiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Dual Approach to Solving SAT in Hardware.

Dinesh D. Narasimharaju, R. S. Suraj Rao, Akshaya Sandeep Waingade, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering.

Cunxi Yu, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Functional Verification of Hardware Dividers using Algebraic Model.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Formal Verification of Integer Dividers: Division by a Constant.

Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Spectral approach to verifying non-linear arithmetic circuits.

Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Fast Algebraic Rewriting Based on And-Inverter Graphs.

Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Formal Analysis of Galois Field Arithmetics - Parallel Verification and Reverse Engineering.

Cunxi Yu, Maciej J. Ciesielski

CoRR, 2018

Rewriting Environment for Arithmetic Circuit Verification.

Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski

Proceedings of the LPAR-22. 22nd International Conference on Logic for Programming, 2018

End-to-End Industrial Study of Retiming.

Cunxi Yu, Chau-Chin Huang, Gi-Joon Nam, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Maciej J. Ciesielski, Giovanni De Micheli

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers.

Tiankai Su, Atif Yasin, Cunxi Yu, Maciej J. Ciesielski

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits.

Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej J. Ciesielski, Daniel E. Holcomb

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis.

Tiankai Su, Cunxi Yu, Atif Yasin, Maciej J. Ciesielski

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Advanced datapath synthesis using graph isomorphism.

Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Reverse engineering of irreducible polynomials in GF(2^m) arithmetic.

Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient parallel verification of Galois field multipliers.

Cunxi Yu, Maciej J. Ciesielski

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Formal Verification of Arithmetic Circuits by Function Extraction.

Cunxi Yu, Walter Brown, Duo Liu, André Rossi, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reverse Engineering of Irreducible Polynomials in GF(2^m) Arithmetic.

Cunxi Yu, Daniel E. Holcomb, Maciej J. Ciesielski

CoRR, 2016

Formal Verification Using Don't-Care and Vanishing Polynomials.

Cunxi Yu, Maciej J. Ciesielski

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Analyzing Imprecise Adders Using BDDs - A Case Study.

Cunxi Yu, Maciej J. Ciesielski

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Automatic word-level abstraction of datapath.

Cunxi Yu, Maciej J. Ciesielski

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

DAG-aware logic synthesis of datapaths.

Cunxi Yu, Maciej J. Ciesielski, Mihir Choudhury, Andrew Sullivan

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Logic Debugging of Arithmetic Circuits.

Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploiting Circuit Duality to Speed up SAT.

Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Verification of arithmetic datapath designs using word-level approach - A case study.

Cunxi Yu, Walter Brown, Maciej J. Ciesielski

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Verification of gate-level arithmetic circuits by function extraction.

Maciej J. Ciesielski, Cunxi Yu, Walter Brown, Duo Liu, André Rossi

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Function Extraction from Arithmetic Bit-Level Circuits.

Maciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning.

Tariq B. Ahmad, Maciej J. Ciesielski

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Fast time-parallel C-based event-driven RTL simulation.

Tariq Bashir Ahmad, Maciej J. Ciesielski

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Fast STA prediction-based gate-level timing simulation.

Tariq B. Ahmad, Maciej J. Ciesielski

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads.

Tariq Bashir Ahmad, Maciej J. Ciesielski

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Arithmetic Bit-Level Verification Using Network Flow Model.

Maciej J. Ciesielski, Walter Brown, André Rossi

Proceedings of the Hardware and Software: Verification and Testing, 2013

FPGA latency optimization using system-level transformations and DFG restructuring.

Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier

Proceedings of the Design, Automation and Test in Europe, 2013

2011

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.

Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski

J. Low Power Electron., 2011

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.

Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Algebraic approach to arithmetic design verification.

Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

A new distributed event-driven gate-level HDL simulation by accurate prediction.

Dusung Kim, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

Temporal parallel simulation: A fast gate-level HDL simulation using higher level models.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the Design, Automation and Test in Europe, 2011

2010

The best constant approximant operators in Lorentz spaces Gamma_{p, w} and their applications.

Maciej J. Ciesielski, Anna Kaminska

J. Approx. Theory, 2010

Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams.

Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009

Optimization of Data-Flow Computations Using Canonical TED Representation.

Maciej J. Ciesielski, Daniel Gomez-Prado, Qian Ren, Jérémie Guillot, Emmanuel Boutillon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

High-Level Dataflow Transformations Using Taylor Expansion Diagrams.

Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon

IEEE Des. Test Comput., 2009

Optimizing data flow graphs to minimize hardware implementation.

Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Simulation Acceleration with HW Re-Compilation Avoidance.

Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Temporal parallel gate-level timing simulation.

Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

A fast two-pass HDL simulation with on-demand dump.

Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Data-flow transformations using Taylor expansion diagrams.

Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs.

Maciej J. Ciesielski, Priyank Kalla, Serkan Askar

IEEE Trans. Computers, 2006

Efficient factorization of DSP transforms using taylor expansion diagrams.

Jérémie Guillot, Emmanuel Boutillon, Qian Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Functional test generation based on word-level SAT.

Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski

J. Syst. Archit., 2005

Design validation of behavioral VHDL descriptions for arbitrary fault models.

Fei Xin, Maciej J. Ciesielski, Ian G. Harris

Proceedings of the 10th European Test Symposium, 2005

Yield-aware Floorplanning.

Zhaojun Wo, Israel Koren, Maciej J. Ciesielski

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

An ILP Formulation for Yield-driven Architectural Synthesis.

Zhaojun Wo, Israel Koren, Maciej J. Ciesielski

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Algorithms for Taylor Expansion Diagrams.

Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Variable ordering for taylor expansion diagrams.

Daniel Gomez-Prado, Qian Ren, Serkan Askar, Maciej J. Ciesielski, Emmanuel Boutillon

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

A new state assignment technique for testing and low power.

Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski

Proceedings of the 41th Design Automation Conference, 2004

2003

Mathematical framework for representing discrete functions as word-level polynomials.

Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski

Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Fast Computation of Data Correlation Using BDDs.

Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski

Proceedings of the 2003 Design, 2003

2002

BDS: a BDD-based logic optimization system.

Congguang Yang, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A comprehensive approach to the partial scan problem using implicitstate enumeration.

Priyank Kalla, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Analytical approach to layout generation of datapath cells.

Maciej J. Ciesielski, Serkan Askar, Samuel Levitin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

High-level design verification using Taylor Expansion Diagrams: first results.

Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification.

Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre

Proceedings of the 2002 Design, 2002

2001

Strategies for solving the Boolean satisfiability problem using binary decision diagrams.

Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski

J. Syst. Archit., 2001

Functional Test Generation using Constraint Logic Programming.

Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre

Proceedings of the SOC Design Methodologies, 2001

Taylor expansion diagrams: a new representation for RTL verification.

Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

LPSAT: a unified approach to RTL satisfiability.

Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Retiming-based factorization for sequential logic optimization.

Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski

ACM Trans. Design Autom. Electr. Syst., 2000

Synthesis for Mixed CMOS/PTl Logic.

Congguang Yang, Maciej J. Ciesielski

Proceedings of the 2000 Design, 2000

A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm.

Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang

Proceedings of the 2000 Design, 2000

BDS: a BDD-based logic optimization system.

Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal

Proceedings of the 37th Conference on Design Automation, 2000

1999

Transistor level placement for full custom datapath cell design.

Durgam Vahia, Maciej J. Ciesielski

Proceedings of the 1999 International Symposium on Physical Design, 1999

BDD Decomposition for Efficient Logic Synthesis.

Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal

Proceedings of the IEEE International Conference On Computer Design, 1999

Analytical approach to custom datapath design.

Serkan Askar, Maciej J. Ciesielski

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.

Priyank Kalla, Maciej J. Ciesielski

Proceedings of the 1999 Design, 1999

1998

Wave-pipelining: a tutorial and research survey.

Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu

IEEE Trans. Very Large Scale Integr. Syst., 1998

A comprehensive approach to the partial scan problem using implicit state enumeration.

Priyank Kalla, Maciej J. Ciesielski

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Reencoding for cycle-time minimization under fixed encoding length.

Balakrishnan Iyer, Maciej J. Ciesielski

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Testability of Sequential Circuits with Multi-Cycle False Path.

Priyank Kalla, Maciej J. Ciesielski

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Intelligent Simulation for Computer Aided Design of Optical Networks.

Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga

Proceedings of the Optical Network Design and Modeling, 1997

1996

Metamorphosis: state assignment by retiming and re-encoding.

Balakrishnan Iyer, Maciej J. Ciesielski

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

FSM Decomposition and Functional Verification of FSM Networks.

Zafar Hasan, Maciej J. Ciesielski

VLSI Design, 1995

Elimination of multi-cycle false paths by state encoding.

Zafar Hasan, Maciej J. Ciesielski

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Forum: Wave-pipelining: Is it Practical?

Wayne P. Burleson, Leonard W. Cotten, Fabian Klass, Maciej J. Ciesielski

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Clock period minimization with wave pipelining.

Donald A. Joy, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Functional verification and simulation of FSM networks.

Zafar Hasan, Maciej J. Ciesielski

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992

PLADE: a two-stage PLA decomposition.

Maciej J. Ciesielski, Seiyang Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Layer assignment for printed circuit boards and integrated circuits.

Donald A. Joy, Maciej J. Ciesielski

Proc. IEEE, 1992

A Fast Partitioning Method for PLA-Based FPGAs.

Zafar Hasan, David Harrison, Maciej J. Ciesielski

IEEE Des. Test Comput., 1992

Finite State Machine Decomposition Using Multiway Partitioning.

Maya K. Yajnik, Maciej J. Ciesielski

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization.

Seiyang Yang, Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Placement for Clock Period Minimization With Multiple Wave Propagation.

Donald A. Joy, Maciej J. Ciesielski

Proceedings of the 28th Design Automation Conference, 1991

A Unified Approach to Input-Output Encoding for FSM State Assignment.

Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio

Proceedings of the 28th Design Automation Conference, 1991

1989

Layer assignment for VLSI interconnect delay minimization.

Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Multiple-valued Boolean minimization based on graph coloring.

Maciej J. Ciesielski, Saeyang Yang, Marek A. Perkowski

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

PLA decomposition with generalized decoders.

Seiyang Yang, Maciej J. Ciesielski

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1987

Digraph Relaxation for 2-Dimensional Placement of IC Blocks.

Maciej J. Ciesielski, Edwin Kinnen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1985

Two-Dimensional Routing for the Silc Silicon Compiler.

Maciej J. Ciesielski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1982

An analytical method for compacting routing area in integrated circuits.

Maciej J. Ciesielski, Edwin Kinnen

Proceedings of the 19th Design Automation Conference, 1982

1981

An optimum layer assignment for routing in ICs and PCBs.

Maciej J. Ciesielski, Edwin Kinnen

Proceedings of the 18th Design Automation Conference, 1981