Maarten Rosmeulen

According to our database1, Maarten Rosmeulen authored at least 17 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Exploring the Reliability Limits for the Z-Pitch Scaling of Molybdenum Inter-Word Line Oxides in 3D NAND.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Investigation of the Impact of Ferroelectricity Boosted Gate Stacks for 3D NAND on Short Time Data Retention and Endurance.
Proceedings of the IEEE International Reliability Physics Symposium, 2024

Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash.
Proceedings of the IEEE International Memory Workshop, 2024

Gate Side Injection Operating Mode for 3D NAND Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2024

A DTCO Framework for 3D NAND Flash Readout.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Enabling 3D NAND Trench Cells for Scaled Flash Memories.
Proceedings of the IEEE International Memory Workshop, 2023

Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering.
Proceedings of the IEEE International Memory Workshop, 2023

Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NAND.
Proceedings of the IEEE International Memory Workshop, 2023

2022

At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells.
Proceedings of the IEEE International Memory Workshop, 2022

High-K incorporated in a SiON tunnel layer for 3D NAND programming voltage reduction.
Proceedings of the IEEE International Memory Workshop, 2022

2021
Reliability of Mo as Word Line Metal in 3D NAND.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.
Proceedings of the IEEE International Memory Workshop, 2021

2018
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification.
Sensors, 2018

2016
Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging.
Sensors, 2016

2007
Characterization of charge trapping in SiO<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub> dielectric stacks by pulsed C-V technique.
Microelectron. Reliab., 2007

2002
An easy-to-use mismatch model for the MOS transistor.
IEEE J. Solid State Circuits, 2002


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