M. Watheq El-Kharashi
Orcid: 0000-0002-6033-733X
According to our database1,
M. Watheq El-Kharashi
authored at least 122 papers
between 2000 and 2024.
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Bibliography
2024
J. Electron. Test., October, 2024
IEEE Trans. Computers, February, 2024
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach.
J. Electron. Test., February, 2024
Apply Balancing Technique Utilizing Standard Cells Decoupling Caps to Mitigate Side-Channel Attacks.
Proceedings of the International Conference on Microelectronics, 2024
2023
Detecting Cyber Attacks In-Vehicle Diagnostics Using an Intelligent Multistage Framework.
Sensors, September, 2023
Des. Autom. Embed. Syst., September, 2023
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation.
ACM Trans. Design Autom. Electr. Syst., July, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023
Proceedings of the International Conference on Microelectronics, 2023
Improved Dynamic Collision Recovery in Wireless Ad-Hoc Networks: System and RTL Modeling.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023
2022
Des. Autom. Embed. Syst., December, 2022
IEEE Access, 2022
An Evaluation Method for Embedded Software Dependability Using QEMU-Based Fault Injection Framework.
Proceedings of the 6th International Conference on System Reliability and Safety, 2022
A Reusable UVM-SystemC Verification Environment for Simulation, Hardware Emulation, and FPGA Prototyping: Case Studies.
Proceedings of the International Conference on Microelectronics, 2022
Optimized FPGA Architecture for Machine Learning Applications using Posit Multipliers.
Proceedings of the International Conference on Microelectronics, 2022
Proceedings of the 5th International Conference on Communications, 2022
Proceedings of the 5th International Conference on Communications, 2022
Privacy Guarantees for Cloud-based State Estimation using Partially Homomorphic Encryption.
Proceedings of the European Control Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Lightweight Diagnostic-based Secure Framework for Electronic Control Units in Vehicles.
Proceedings of the International Symposium on Networks, Computers and Communications, 2021
Proceedings of the International Conference on Microelectronics, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
NoC<sup>2</sup>: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems.
IEEE Access, 2020
Proceedings of the 32nd International Conference on Microelectronics, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
2019
An ultrafast neural network-based hardware acceleration for nonlinear systems' simulators.
Comput. Electr. Eng., 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Reduction of Variations Using Chemometric Model Transfer: A Case Study Using FT-NIR Miniaturized Sensors.
Proceedings of the International Conference on Advanced Machine Learning Technologies and Applications, 2019
2018
J. Circuits Syst. Comput., 2018
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018
2017
A power-optimized, area-efficient implementation of Connection-Then-Credit NoC physical layer.
Microelectron. J., 2017
CoRR, 2017
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
Proceedings of the Natural Language Processing and Information Systems, 2017
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017
Proceedings of the 14th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2017) / 12th International Conference on Future Networks and Communications (FNC 2017) / Affiliated Workshops, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Microprocess. Microsystems, 2016
A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories.
J. Circuits Syst. Comput., 2016
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016
SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification.
Proceedings of the 11th International Design & Test Symposium, 2016
Proceedings of the 11th International Conference on Future Networks and Communications (FNC 2016) / The 13th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2016) / Affiliated Workshops, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
ASU: An Experimental Study on Applying Deep Learning in Twitter Named Entity Recognition.
Proceedings of the 2nd Workshop on Noisy User-generated Text, 2016
2015
Microelectron. J., 2015
Comput. Electr. Eng., 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Traffic analysis of multi-core body sensor networks based on Wireless NoC infrastructure.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Pin-Count and Wire Length Optimization for Electrowetting-on-Dielectric Chips: A Metaheuristics-Based Routing Algorithm.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015
2014
Microprocess. Microsystems, 2014
Microprocess. Microsystems, 2014
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.
Proceedings of the 15th International Microprocessor Test and Verification Workshop, 2014
The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs.
Proceedings of the 2014 International Workshop on Network on Chip Architectures, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014
Proceedings of the 28th International Conference on Advanced Information Networking and Applications Workshops, 2014
2013
Microprocess. Microsystems, 2013
IET Comput. Digit. Tech., 2013
An embedded implementation of the Generalized Predictive Control algorithm applied to automotive active suspension systems.
Comput. Electr. Eng., 2013
Authenticated key exchange protocol using neural cryptography with secret boundaries.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Graph-based approach for software allocation in automotive networked embedded systems: A partition-and-map algorithm.
Proceedings of the 2013 Forum on specification and Design Languages, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012
2011
Int. J. Circuit Theory Appl., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Embed. Syst. Lett., 2010
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010
Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Networks-on-chip topology optimization subject to power, delay, and reliability constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 5th International Design and Test Workshop, 2010
2009
Power optimization for application-specific networks-on-chips: A topology-based approach.
Microprocess. Microsystems, 2009
J. Netw. Comput. Appl., 2009
Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification.
Comput. Networks, 2009
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009
2008
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695].
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Prioritized e-mail servicing to reduce non-spam delay and loss: A performance analysis.
Int. J. Netw. Manag., 2008
Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation.
IET Comput. Digit. Tech., 2008
J. Res. Pract. Inf. Technol., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Application-specific networks-on-chip topology customization using network partitioning.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
J. Circuits Syst. Comput., 2007
A Platform Approach for Hardware/Software Co-Design with Support for RTOS-Based Systems.
J. Circuits Syst. Comput., 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Multidimens. Syst. Signal Process., 2006
An FPGA implementation of the flexible triangle search algorithm for block based motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the Correct Hardware Design and Verification Methods, 2005
2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
2002
IEEE Trans. Educ., 2002
The JAFARDD processor: a Java architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing.
IEEE Trans. Consumer Electron., 2002
2001
SIGARCH Comput. Archit. News, 2001
A robust stack folding approach for Java processors: an operand extraction-based algorithm.
J. Syst. Archit., 2001
2000
A quantitative study for Java microprocessor architectural requirements. Part II: high-level language support.
Microprocess. Microsystems, 2000
A quantitative study for Java microprocessor architectural requirements. Part I: Instruction set design.
Microprocess. Microsystems, 2000