M. Rullán

According to our database1, M. Rullán authored at least 5 papers between 1993 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1994
An Approach to the Development of a IDDQ Testable Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Testability enhancement using physical design rules in a CMOS cell library.
Microprocess. Microprogramming, 1993

Layout-level design for testability rules for a CMOS cell library.
Proceedings of the European Design Automation Conference 1993, 1993

Layout Level Design for Testability Strategy Applied to a CMOS Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993


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