M. Ray Mercer

According to our database, M. Ray Mercer authored at least 71 papers between 1981 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2005

An optimal test pattern selection method to improve the defect coverage.

Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets.

Jennifer Dworak, David Dorsey, Amy Wang, M. Ray Mercer

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects.

Jennifer Dworak, James Wingfield, M. Ray Mercer

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects.

Jennifer Dworak, Brad Cobb, James Wingfield, M. Ray Mercer

Proceedings of the 2004 Design, 2004

2003

Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.

Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Function-Based Dynamic Compaction and its Impact on Test Set Sizes.

James Wingfield, Jennifer Dworak, M. Ray Mercer

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method.

Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.

Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults.

Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael R. Grimaila, M. Ray Mercer

Proceedings of the 2002 Design, 2002

Directed-Binary Search in Logic BIST Diagnostics.

Rohit Kapur, Thomas W. Williams, M. Ray Mercer

Proceedings of the 2002 Design, 2002

Enhancing test efficiency for delay fault testing using multiple-clocked schemes.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the 39th Design Automation Conference, 2002

2001

Defect-Oriented Testing and Defective-Part-Level Prediction.

Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang

IEEE Des. Test Comput., 2001

2000

Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.

Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.

Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.

Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.

Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Multi-Level Logic Minimization through Fault Dictionary Analysis.

Ronald W. Mehler, M. Ray Mercer

Proceedings of the IEEE International Conference On Computer Design, 1999

1996

Efficient logic-level timing analysis using constraint-guided critical path search.

Chanhee Oh, M. Ray Mercer

IEEE Trans. Very Large Scale Integr. Syst., 1996

I_DDQ Test: Sensitivity Analysis of Scaling.

Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Using Target Faults To Detect Non-Tartget Defects.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Better ATPG Algorithm and Its Design Principles.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Using Functional Information and Strategy Switching in Sequential ATPG.

Jaehong Park, M. Ray Mercer

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Iddq Testing for High Performance CMOS - The Next Ten Years.

Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly

Proceedings of the 1996 European Design and Test Conference, 1996

1995

On the decline of testing efficiency as fault coverage approaches 100%.

Li-C. Wang, M. Ray Mercer, Sophia W. Kao, Thomas W. Williams

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On Efficiently and Reliably Achieving Low Defective Part Levels.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Enhanced testing performance via unbiased test sets.

Li-C. Wang, M. Ray Mercer, Thomas W. Williams

Proceedings of the 1995 European Design and Test Conference, 1995

Improved sequential ATPG using functional observation information and new justification methods.

Jaehong Park, Chanhee Oh, M. Ray Mercer

Proceedings of the 1995 European Design and Test Conference, 1995

1994

Least Upper Bounds an OBDD Sizes.

Mark A. Heap, M. Ray Mercer

IEEE Trans. Computers, 1994

Limitations in predicting defect level based on stuck-at fault coverage.

Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis.

Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Combinational circuit ATPG using binary decision diagrams.

Sanjay Srinivasan, Gnanasekaran Swaminathan, James H. Aylor, M. Ray Mercer

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Switch-Level ATPG Using Constraint-Guided Line Justification.

Eun Sei Park, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

An Efficient Symbolic Design Verification System.

Jaehong Park, M. Ray Mercer

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

An efficient delay test generation system for combinational logic circuits.

Eun Sei Park, M. Ray Mercer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

The Total Delay Fault Model and Statistical Delay Fault Coverage.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Trans. Computers, 1992

Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.

Rohit Kapur, M. Ray Mercer

IEEE Trans. Computers, 1992

The roles of controllability and observability in design for test.

Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

All Tests for a Fault Are Not Equally Valuable for Defect Detection.

Rohit Kapur, Jaehong Park, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A Synthesis Algorithm for Two-Level XOR Based Circuits.

Mark A. Heap, William A. Rogers, M. Ray Mercer

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

ETA: electrical-level timing analysis.

Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Functional Approaches to Generating Orderings for Efficient Symbolic Representations.

M. Ray Mercer, Rohit Kapur, Don E. Ross

Proceedings of the 29th Design Automation Conference, 1992

1991

Exact ordered binary decision diagram size when representing classes of symmetric functions.

Don E. Ross, Kenneth M. Butler, M. Ray Mercer

J. Electron. Test., 1991

Testing and Design Verification of Electronic Components.

M. Ray Mercer

Computer, 1991

Delay Testing Quality in Timing-Optimized Designs.

Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Fast functional evaluation of candidate OBDD variable orderings.

Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer

Proceedings of the conference on European design automation, 1991

The Interdependence Between Delay-Optimization of Synthesized Networks and Testing.

Thomas W. Williams, Bill Underwood, M. Ray Mercer

Proceedings of the 28th Design Automation Conference, 1991

Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.

Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer

Proceedings of the 28th Design Automation Conference, 1991

1990

Guest Editorial: ITC 20th Anniversary.

M. Ray Mercer

IEEE Des. Test Comput., 1990

The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design.

Kenneth M. Butler, M. Ray Mercer

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

A statistical model for delay-fault testing.

Eun Sei Park, M. Ray Mercer, Thomas W. Williams

IEEE Des. Test, 1989

A Deterministic Approach to Adjacency Testing for Delay Faults.

C. Thomas Glover, M. Ray Mercer

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Algorithms for automatic test pattern generation.

Tom E. Kirkland, M. Ray Mercer

IEEE Des. Test, 1988

D^3FS: A Demand Driven Deductive Fault Simulator.

Steven P. Smith, Bill Underwood, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1988, 1988

Statistical Delay Fault Coverage and Defect Level for Delay Faults.

Eun Sei Park, Thomas W. Williams, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1988, 1988

A Method of Delay Fault Test Generation.

C. Thomas Glover, M. Ray Mercer

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology.

Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Demand Driven Simulation: BACKSIM.

Steven P. Smith, M. Ray Mercer, B. Brodk

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

A Topological Search Algorithm for ATPG.

Tom E. Kirkland, M. Ray Mercer

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits.

Ki Soo Hwang, M. Ray Mercer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Logic Elements for Universally Testable Circuits.

M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1986, 1986

Informed Test Generation Guidance Using Partially Specified Fanout Constraints.

Ki Soo Hwang, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1986, 1986

Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm.

Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood

Proceedings of the Proceedings International Test Conference 1986, 1986

Deterministic Versus Random Testing.

Vishwani D. Agrawal, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1986, 1986

A Two-Level Guidance Heuristic for ATPG.

Tom E. Kirkland, M. Ray Mercer

Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

1985

Built-In Self Test Input Generator for Programmable Logic Arrays.

John Salick, Bill Underwood, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1985, 1985

CADTOOLS: a CAD algorithm development system.

Eric Schell, M. Ray Mercer

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Correlating Testability with Fault Detection.

Bill Underwood, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1984, 1984

1983

Testing Issues at the University of Texas.

M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1983, 1983

1982

Testability Measures : What Do They Tell Us ?

Vishwani D. Agrawal, M. Ray Mercer

Proceedings of the Proceedings International Test Conference 1982, 1982

1981

Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation.

M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman

Proceedings of the Proceedings International Test Conference 1981, 1981