M. P. J. Stevens

According to our database1, M. P. J. Stevens authored at least 16 papers between 1990 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2003
A scalable single-chip multi-processor architecture with on-chip RTOS kernel.
J. Syst. Archit., 2003

2002
Concurrent Support of Higher-Layer Protocols over WDM.
Photonic Netw. Commun., 2002

2001
Object-oriented modelling and specification using SHE.
Comput. Lang., 2001

1999
System Level Models for Real-Time Communication.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
System Level Modelling for Hardware/Software Systems.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Design-For-Debug in Hardware/Software Co-Design.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture Design.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

1994
System-Level Testability of Hardware/Software Systems.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
TL: A system specification system.
Microprocess. Microprogramming, 1993

1992
Task level specification and communication.
Microprocess. Microprogramming, 1992

1991
Compilation techniques for a high level language processor.
Microprocessing and Microprogramming, 1991

Object oriented system analysis for VLSI.
Microprocessing and Microprogramming, 1991

Task level behavioral hardware description.
Microprocessing and Microprogramming, 1991

1990
System level VLSI design.
Microprocessing and Microprogramming, 1990

Pipelining a memory based CISC processor.
Microprocessing and Microprogramming, 1990

Designing high performance instruction caches in VLSI.
Microprocessing and Microprogramming, 1990


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