M. Nirmala Devi

According to our database, M. Nirmala Devi authored at least 27 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors.

Karthigha Balamurugan, M. Nirmala Devi, M. Jayakumar

J. Electr. Comput. Eng., 2023

PUF based on chip comparison technique for trustworthy scan design data security against side channel attack.

Shiny Mukkath I., Nirmala Devi M.

Int. J. Cloud Comput., 2023

Hexagonal-Triangular Combinatorial Structure Based Dual-Band Circularly Polarized Patch Antenna for GAGAN Receivers.

C. Sahana, Nirmala Devi Manickam, M. Jayakumar

IEEE Access, 2023

Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique.

Vaishnavi Sankar, Balachander Sathianarayanan, Nirmala Devi Manickam, M. Jayakumar

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application.

M. I. Shiny, M. Nirmala Devi

Mob. Networks Appl., 2022

Feature-based augmentation and classification for tabular data.

Balachander Sathianarayanan, Yogesh Chandra Singh Samant, Prahalad S. Conjeepuram Guruprasad, Varshin B. Hariharan, Nirmala Devi Manickam

CAAI Trans. Intell. Technol., 2022

Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices.

Vaishnavi Sankar, M. Nirmala Devi, M. Jayakumar

IEEE Access, 2022

Obviating Multiple Attacks with Enhanced Logic Locking.

Paul Anu, N. Mohankumar, M. Nirmala Devi

Proceedings of the 2022 Fourteenth International Conference on Contemporary Computing, 2022

2021

Fault detection in satellite power system using convolutional neural network.

M. Ganesan, R. Lavanya, M. Nirmala Devi

Telecommun. Syst., 2021

2019

Secured Hardware Design with Locker-Box Against a Key-Guessing Attacks.

R. Sree Ranjani, M. Nirmala Devi

J. Low Power Electron., 2019

Realization of Re-configurable True Random Number Generator on FPGA.

M. Priyatharishini, M. Nirmala Devi

Proceedings of the Security in Computing and Communications - 7th International Symposium, 2019

2018

Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls.

Arun Kumar Sundar Rajan, Armin Feucht, Lothar Gamer, Idriz Smaili, M. Nirmala Devi

J. Syst. Archit., 2018

Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks.

Sree Ranjani Rajendran, M. Nirmala Devi

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Key Retrieval from AES Architecture Through Hardware Trojan Horse.

Sivappriya Manivannan, N. Nalla Anandakumar, M. Nirmala Devi

Proceedings of the Security in Computing and Communications - 6th International Symposium, 2018

Analysis of Circuits for Security Using Logic Encryption.

Bandarupalli Chandini, M. Nirmala Devi

Proceedings of the Security in Computing and Communications - 6th International Symposium, 2018

A Novel Logical Locking Technique Against Key-Guessing Attacks.

Sree Ranjani Rajendran, M. Nirmala Devi

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Capacity Analysis of Correlated MIMO in GEOSAT Downlink Land Mobile System.

S. Jaiyant Gopal, J. Ramnarayan, S. Kirthiga, M. Jayakumar, M. Nirmala Devi, R. Gandhiraj, Subhash Chandra Bera

Proceedings of the 2018 International Conference on Advances in Computing, 2018

2017

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.

Rajat Subhra Chakraborty, Samuel Pagliarini, Jimson Mathew, Sree Ranjani Rajendran, M. Nirmala Devi

IEEE Trans. Emerg. Top. Comput., 2017

Hardware Trojan Detection Using Effective Test Patterns and Selective Segmentation.

K. Atchuta Sashank, Hari Sivarami Reddy, P. Pavithran, M. S. Akash, M. Nirmala Devi

Proceedings of the Security in Computing and Communications - 5th International Symposium, 2017

2015

Detection and Diagnosis of Hardware Trojan Using Power Analysis.

Eknadh Vaddi, Karthik Gaddam, Rahul Karthik Maniam, Sai Abhishek Mallavajjala, Srinivasulu Dasari, M. Nirmala Devi

Proceedings of the Security in Computing and Communications, 2015

Malicious Circuit Detection for Improved Hardware Security.

R. Bharath, G. Arun Sabari, Dhinesh Ravi Krishna, Arun Prasathe, K. Harish, N. Mohankumar, M. Nirmala Devi

Proceedings of the Security in Computing and Communications, 2015

2014

Design and analysis of GaN HEMT based LNA with CPW matching.

S. Sarathkrishna, Karthigha Balamurugan, M. Nirmala Devi, M. Jayakumar

Proceedings of the Eleventh International Conference on Wireless and Optical Communications Networks, 2014

Deterministic seed selection and pattern reduction in Logic BIST.

Ramesh Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2012

A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power.

P. R. Sruthi, M. Nirmala Devi

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

2010

PSO learning on artificial neural networks.

Nisha Haridas, M. Nirmala Devi

Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India, 2010

2008

FPGA Realization of Activation Function for Artificial Neural Networks.

Venakata Saichand, M. Nirmala Devi, S. Arumugam, N. Mohankumar

Proceedings of the Eighth International Conference on Intelligent Systems Design and Applications, 2008

A Modified Genetic Algorithm for Evolution of Neural Network in Designing an Evolutionary Neuro-Hardware.

N. Mohankumar, B. Bhuvan, M. Nirmala Devi, S. Arumugam

Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008