M. Mohamed Asan Basiri

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

2023

Efficient FPGA Implementations of Lifting based DWT using Partial Reconfiguration.

[BibT_eX]

[DOI]

PVSR Bharadwaja

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

High Throughput Circuit Design of Flash Type Analog to Digital Converter.

[BibT_eX]

[DOI]

Shivalasya Chinthala

Proceedings of the 5th International Conference on Recent Advances in Information Technology, 2023

High Throughput Circuit Designs of Digital to Analog Converter.

[BibT_eX]

[DOI]

M. V. D. B. Anjaneya

Proceedings of the 5th International Conference on Recent Advances in Information Technology, 2023

2022

Efficient VLSI architecture of 3D discrete transformation.

[BibT_eX]

[DOI]

Integr., 2022

Versatile Architectures of Artificial Neural Network with Variable Capacity.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2022

Low Cost Hardware Design of ECC Scalar Multiplication.

[BibT_eX]

[DOI]

Hariveer Inumarty

Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

2021

Hardware based Order Book Design in High Frequency Algo Trading.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Hardware based Entropy Calculation in Crypto Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020

Efficient VLSI architectures of lifting based 3D discrete wavelet transform.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2020

Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations.

[BibT_eX]

[DOI]

Hariveer Inumarty

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Discrete Orthogonal Multi-transform on Chip (DOMoC).

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2019

LFSR based versatile divider architectures for BCH and RS error correction encoders.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

Asynchronous hardware implementations for crypto primitives.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Flexible Adaptive FIR Filter Designs Using LMS Algorithm.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Formal Hardware Verification of InfoSec Primitives.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

Low power hardware implementations for network packet processing elements.

[BibT_eX]

[DOI]

Integr., 2018

An Efficient VLSI Architecture for Convolution Based DWT Using MAC.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017

Flexible VLSI architectures for Galois field multipliers.

[BibT_eX]

[DOI]

Integr., 2017

Quadruple throughput fixed point quarter precision multiply accumulate circuit design.

[BibT_eX]

[DOI]

S. K. Noor Mohammad

IET Comput. Digit. Tech., 2017

High Performance Integer DCT Architectures for HEVC.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

High speed multiplexer design using tree based decomposition algorithm.

[BibT_eX]

[DOI]

Microelectron. J., 2016

An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform.

[BibT_eX]

[DOI]

Integr., 2016

An Efficient VLSI Architecture for Discrete Hadamard Transform.

[BibT_eX]

[DOI]

S. K. Noor Mahammad

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Hardware optimizations for crypto implementations (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015

Configurable Folded IIR Filter Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2014

An Efficient Hardware-Based Higher Radix Floating Point MAC Design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

Memory Based Multiplier Design in Custom and FPGA Implementation.

[BibT_eX]

[DOI]