M. Hüsrev Cilasun

Orcid: 0000-0002-5421-1159

According to our database1, M. Hüsrev Cilasun authored at least 27 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization.
Dataset, January, 2024

On Error Correction for Nonvolatile Processing-In-Memory.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

On Gate Flip Errors in Computing-In-Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Experimental demonstration of magnetic tunnel junction-based computational random-access memory.
CoRR, 2023

3SAT on an All-to-All-Connected CMOS Ising Solver Chip.
CoRR, 2023

On Endurance of Processing in (Nonvolatile) Memory.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2023

2022
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions.
ACM Trans. Embed. Comput. Syst., September, 2022

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM.
IEEE Trans. Emerg. Top. Comput., 2022

Error Detection and Correction for Processing in Memory (PiM).
CoRR, 2022

FPGA-accelerated simulation of variable latency memory systems.
Proceedings of the 2022 International Symposium on Memory Systems, 2022

2021
Spiking Neural Networks in Spintronic Computational RAM.
ACM Trans. Archit. Code Optim., 2021

Towards Homomorphic Inference Beyond the Edge.
CoRR, 2021

Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator.
CoRR, 2021

Cryogenic PIM: Challenges & Opportunities.
IEEE Comput. Archit. Lett., 2021

Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

CAMeleon: Reconfigurable B(T)CAM in Computational RAM.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM).
CoRR, 2020

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018
Exploiting Reversible Computing for Latent-Fault-Free Error Detecting/Correcting CMOS Circuits.
IEEE Access, 2018

Fast DST optimizations for intra-frame coding.
Proceedings of the 26th Signal Processing and Communications Applications Conference, 2018

Coding Gain Optimized 8-Point DST with Fast Algorithm for Intra-frames in Video Coding.
Proceedings of the 26th European Signal Processing Conference, 2018

2017
Synthesis and fundamental energy analysis of fault-tolerant CMOS circuits.
Proceedings of the 14th International Conference on Synthesis, 2017

2016
Generalized Multiple Counting Jacobsthal Sequences of Fermat Pseudoprimes.
J. Integer Seq., 2016

Deep learning based autonomous direction estimation.
Proceedings of the 24th Signal Processing and Communication Application Conference, 2016

A deep learning approach to EEG based epilepsy seizure determination.
Proceedings of the 24th Signal Processing and Communication Application Conference, 2016


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