M. Enamul Amyeen

According to our database, M. Enamul Amyeen authored at least 32 papers between 1999 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Generating Storage-Aware Test Sets Targeting Several Fault Models.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2022

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Logic Diagnosis with Hybrid Fail Data.

Irith Pomeranz, M. Enamul Amyeen

ACM Trans. Design Autom. Electr. Syst., 2021

Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume.

Irith Pomeranz, M. Enamul Amyeen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2018

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests.

Naixing Wang, Irith Pomeranz, Brady Benware, M. Enamul Amyeen, Srikanth Venkataraman

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017

Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction.

Shraddha Bodhe, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman

IEEE Trans. Very Large Scale Integr. Syst., 2017

Test Modification for Reduced Volumes of Fail Data.

Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman

ACM Trans. Design Autom. Electr. Syst., 2017

Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure.

Srikanth Venkataraman, Irith Pomeranz, Shraddha Bodhe, M. Enamul Amyeen

Proceedings of the IEEE International Test Conference, 2017

2016

Diagnostic Fail Data Minimization Using an N-Cover Algorithm.

Shraddha Bodhe, M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman

IEEE Trans. Very Large Scale Integr. Syst., 2016

Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm.

Shraddha Bodhe, M. Enamul Amyeen, Clariza Galendez, Houston Mooers, Irith Pomeranz, Srikanth Venkataraman

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Diagnostic resolution improvement through learning-guided physical failure analysis.

Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen

Proceedings of the 2016 IEEE International Test Conference, 2016

A novel diagnostic test generation methodology and its application in production failure isolation.

M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma

Proceedings of the 2016 IEEE International Test Conference, 2016

A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction.

M. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Innovative practices session 5C: Advancements in test -keeping moore moving!

M. Enamul Amyeen

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014

Built-in generation of functional broadside tests considering primary input constraints.

Bo Yao, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2011

Logic BIST silicon debug and volume diagnosis methodology.

M. Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Defect diagnosis based on DFM guidelines.

Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

2009

Microprocessor system failures debug and fault isolation methodology.

M. Enamul Amyeen, Srikanth Venkataraman, Mun Wai Mak

Proceedings of the 2009 IEEE International Test Conference, 2009

2008

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects.

Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Using Scan-Dump Values to Improve Functional-Diagnosis Methodology.

Vishnu C. Vimjam, M. Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Testing for systematic defects based on DFM guidelines.

Dongok Kim, M. Enamul Amyeen, Srikanth Venkataraman, Irith Pomeranz, Swagato Basumallick, Berni Landau

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Dominance Based Analysis for Large Volume Production Fail Diagnosis.

Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive.

Ruifeng Guo, Subhasish Mitra, M. Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Improving Precision Using Mixed-level Fault Diagnosis.

M. Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman

Proceedings of the 2006 IEEE International Test Conference, 2006

2004

An Experimental Study of N-Detect Scan ATPG Patterns on a Processor.

Srikanth Venkataraman, Srihari Sivaraj, M. Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.

Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor.

M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Fault equivalence identification in combinational circuits using implication and evaluation techniques.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.

Xiaoming Yu, M. Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

2002

Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits.

M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

1999

Implication and Evaluation Techniques for Proving Fault Equivalence.

M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999