M. D. Arafat Kabir

According to our database, M. D. Arafat Kabir authored at least 10 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs.

Ehsan Kabir, M. D. Arafat Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang

CoRR, 2024

IMAGine: An In-Memory Accelerated GEMV Engine Overlay.

M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

The BRAM is the Limit: Shattering Myths, Shaping Standards, and Building Scalable PIM Accelerators.

M. D. Arafat Kabir, Tendayi Kamucheka, Nathaniel Fredricks, Joel Mandebi, Jason D. Bakos, Miaoqing Huang, David Andrews

Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024

2023

FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?

M. D. Arafat Kabir, Ehsan Kabir, Joshua Hollis, Eli Levy-Mackay, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays.

M. D. Arafat Kabir, Joshua Hollis, Atiyehsadat Panahi, Jason D. Bakos, Miaoqing Huang, David Andrews

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2021

Holistic and In-Context Design Flow for 2.5D Chiplet-Package Interaction Co-Optimization.

M. D. Arafat Kabir, Weishiun Hung, Tsung-Yi Ho, Yarui Peng

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design.

M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Holistic 2.5D Chiplet Design Flow: A 65nm Shared-Block Microcontroller Case Study.

M. D. Arafat Kabir, Yarui Peng

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design.

M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Chiplet-Package Co-Design For 2.5D Systems Using Standard ASIC CAD Tools.

M. D. Arafat Kabir, Yarui Peng

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020